View PSD835G2V-90U_5961404.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/98 preliminary data may 2004 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. psd835g2v flash psd, 3v supply, for 8-bit mcus 4mbit + 256 kbit dual flash memories and 64kbit sram features summary flash in-system programmable (isp) peripheral for 8-bit mcus dual bank flash memories ? 4 mbits of primary flash memory (8 uniform sectors, 64kbyte) ? 256 kbits of secondary flash memory with 4 sectors ? concurrent operation: read from one memory while erasing and writing the other 64 kbit of battery-backed sram 52 reconfigurable i/o ports enhanced jtag serial port pld with macrocells ? over 3000 gates of pld: cpld and dpld ? cpld with 16 output macrocells (omcs) and 24 input macrocells (imcs) ? dpld - user defined internal chip select decoding 52 individually configurable i/o port pins they can be used for the following functions: ? mcu i/os ?pld i/os ? latched mcu address output ? special function i/os. ? i/o ports may be configured as open-drain outputs. in-system programming (isp) with jtag ? built-in jtag compliant serial port allows full-chip in-system programmability ? efficient manufacturing allow easy product testing and programming ? use low cost flashlink cable with pc page register ? internal page register that can be used to expand the microcontroller address space by a factor of 256 programmable power management figure 1. package high endurance: ? 100,000 erase/write cycles of flash memory ? 1,000 erase/write cycles of pld ? 15 year data retention 3v to 3.6v single supply voltage standby current as low as 25a memory speed ? 90ns flash memory and sram access time for v cc = 3.0v to 3.6v ? 120ns flash memory and sram access time for v cc = 3.0v to 3.6v tqfp80 (u)
psd835g2v 2/98 table of contents features summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 in-system programming (isp) via jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 in-application programming (iap). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 psdsoft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 psd architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 page register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 mcu bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 jtag port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 in-application re-programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 psd register description and address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 detailed operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 primary flash memory and secondary flash memory description . . . . . . . . . . . . . . . . . . . . . 22 memory block select signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 upper and lower block in main flash sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ready/busy (pe4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 memory operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read primary flash identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read memory sector protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read the erase/program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 data polling flag (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 toggle flag (dq6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 error flag (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 erase time-out flag (dq3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/98 psd835g2v programming flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 erasing flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 flash bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 flash sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 suspend sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 resume sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 flash memory sector protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 reset flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 reset (r eset) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 sector select and sram select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 memory select configuration for mcus with separate program and data spaces . . . . . . . . 32 configuration modes for mcus with separate program and data spaces . . . . . . . . . . . . . . . 33 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 memory id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 the turbo bit in psd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 decode pld (dpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 complex pld (cpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 output macrocell (omc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 product term allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 the omc mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 the output enable of the omc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 input macrocells (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 external chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 mcu bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 psd interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 psd interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 mcu bus interface examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 80c31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 80c251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 80c51xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 68hc11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
psd835g2v 4/98 i/o ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 general port architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 mcu i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 pld i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 address out mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 address in mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 peripheral i/o mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 jtag in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 port configuration registers (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 drive select register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 data in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 data out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 output macrocells (omc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 omc mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 input macrocells (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 enable out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ports a,b and c ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 port d ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 port e ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 port f ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 port g ? functionality and structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 automatic power-down (apd) unit and power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 pld power management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 psd chip select input (csi, pd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 i/o pin, register and pld status at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 reset of flash memory erase and program cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 programming in-circuit using the jtag/isp interface . . . . . . . . . . . . . . . . . . . . . . . . . . 73 standard jtag signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 jtag extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 security and flash memory protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5/98 psd835g2v ac/dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ac and dc parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 appendix a.pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
psd835g2v 6/98 summary description the psd family of memory systems for microcon- trollers (mcus) brings in-system-programmability (isp) to flash memory and programmable logic. the result is a simple and flexible solution for em- bedded designs. psd devices combine many of the peripheral functions found in mcu based ap- plications. the cpld in the psd devices features an opti- mized macrocell logic architecture. the psd mac- rocell was created to address the unique requirements of embedded system designs. it al- lows direct connection between the system ad- dress/data bus, and the internal psd registers, to simplify communication between the mcu and other supporting devices. the psd family offers two methods to program the psd flash memory while the psd is soldered to the circuit board: in-system programming (isp) via jtag, and in-application programming (iap). in-system programming (isp) via jtag an ieee 1149.1 compliant jtag in-system pro- gramming (isp) interface is included on the psd enabling the entire device (flash memories, pld, configuration) to be rapidly programmed while sol- dered to the circuit board. this requires no mcu participation, which means the psd can be pro- grammed anytime, even when completely blank. the innovative jtag interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: first time programming. how do i get firmware into the flash memory the very first time? jtag is the answer. program the blank psd with no mcu involvement. inventory build-up of pre-programmed devic- es. how do i maintain an accurate count of pre- programmed flash memory and pld devices based on customer demand? how many and what version? jtag is the answer. build your hardware with blank psds soldered directly to the board and then custom program just before they are shipped to the customer. no more labels on chips, and no more wasted inventory. expensive sockets. how do i eliminate the need for expensive and unreliable sockets? jtag is the answer. solder the psd directly to the circuit board. program first time and subsequent times with jtag. no need to handle devices and bend the fragile leads. in-application programming (iap) two independent flash memory arrays are includ- ed so that the mcu can execute code from one while erasing and programming the other. robust product firmware updates in the field are possible over any communications channel (can, ether- net, uart, j1850, etc.) using this unique architec- ture. designers are relieved of these problems: simultaneous read and write to flash memo- ry. how can the mcu program the same memory from which it is executing code? it cannot. the psd allows the mcu to operate the two flash memory blocks concurrently, reading code from one while erasing and programming the other dur- ing iap. complex memory mapping. how can i map these two memories efficiently? a programmable decode pld (dpld) is embedded in the psd. the concurrent psd memories can be mapped anywhere in mcu address space, segment by segment with extremely high address resolution. as an option, the secondary flash memory can be swapped out of t he system memory map when iap is complete. a built-in page register breaks the mcu address limit. separate program and data space. how can i write to flash memory while it resides in program space during field firmware updates? my 80c51 will not allow it. the psd provides means to re- classify flash memory as data space during iap, then back to program space when complete. psdsoft psdsoft, a software development tool from st, guides you through the design process step-by- step making it possible to complete an embedded mcu design capable of isp/iap in just hours. se- lect your mcu and psdsoft takes you through the remainder of the design with point and click entry, covering psd selection, pin definitions, program- mable logic inputs and outputs, mcu memory map definition, ansi-c code generation for your mcu, and merging your mcu firmware with the psd de- sign. when complete, two different device pro- grammers are supported directly from psdsoft: flashlink (jtag) and psdpro.
7/98 psd835g2v figure 2. tqfp80 connections 60 cntl1 59 cntl0 58 pa7 57 pa6 56 pa5 55 pa4 54 pa3 53 pa2 52 pa1 51 pa0 50 gnd 49 gnd 48 pc7 47 pc6 46 pc5 45 pc4 44 pc3 43 pc2 42 pc1 41 pc0 pd2 pd3 ad0 ad1 ad2 ad3 ad4 gnd v cc ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pd1 pd0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 gnd v cc pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 v cc gnd pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 reset cntl2 ai04943
psd835g2v 8/98 table 1. pin description (for the tqfp80 package) pin name pin type description adio 0-7 3-7- 10-12 i/o this is the lower address/data port. connect your mcu address or address/data bus according to the following rules: if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect ad0-ad7 to this port. if your mcu does not have a multiplexed address/data bus, connect a0-a7 to this port. if you are using an 80c51xa in burst mode, connect a4/d0 through a11/d7 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. adio 8-15 13-20 i/o this is the upper address/data port. connect your mcu address or address/data bus according to the following rules: if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect a8-a15 to this port. if your mcu does not have a multiplexed address/data bus, connect a8-a15 to this port. if you are using an 80c251 in page mode, connect ad8-ad15 to this port. if you are using an 80c51xa in burst mode, connect a12-a19 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. cntl 0 59 i the following control signals can be connected to this port, based on your mcu: w r ? active low write strobe input. r_w ? active high read/active low write input. this port is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl 1 60 i the following control signals can be connected to this port, based on your mcu: r d ? active low read strobe input. e ? e clock input. d s ? active low data strobe input. p sen ? connect psen to this port when it is being used as an active low read signal. for example, when the 80c251 outputs more than 16 address bits, psen is actually the read signal. this port is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl 2 40 i this port can be used to input the psen (program select enable) signal from any mcu that uses this signal for code exclusively. if your mcu does not output a program select enable signal, this port can be used as a generic input. this port is connected to the plds as input.
9/98 psd835g2v reset 39 i active low input. resets i/o ports, pld macrocells and some of the configuration registers and jtag registers. must be low at power-up. reset also aborts the flash programming/erase cycle that is in progress. pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 58 57 56 55 54 53 52 51 i/o cmos or open drain these pins make up port a. these port pins are configurable and can have the following functions: mcu i/o ? write to or read from a standard output or input port. cpld macrocell (mcella0-7) outputs. inputs to the plds. latched, transparent or registered pld input. pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 68 67 66 65 64 63 62 61 i/o cmos or open drain these pins make up port b. these port pins are configurable and can have the following functions: mcu i/o ? write to or read from a standard output or input port. cpld macrocell (mcellb0-7) output. inputs to the plds. latched, transparent or registered pld input. pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 48 47 46 45 44 43 42 41 i/o cmos or open drain these pins make up port c. these port pins are configurable and can have the following functions: mcu i/o ? write to or read from a standard output or input port. external chip select (ecs0-7) output. latched, transparent or registered pld input. pd0 79 i/o cmos or open drain pd0 pin of port d. this port pin can be configured to have the following functions: ale/as input latches addresses on adio0-adio15 pins. as input latches addresses on adio0-adio15 pins on the rising edge. input to the plds. transparent pld input. pd1 80 i/o cmos or open drain pd1 pin of port d. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. input to the plds. clkin ? clock input to the cpld macrocells, the apd unit?s power-down counter, and the cpld and array. pd2 1 i/o cmos or open drain pd2 pin of port d. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. input to the plds. psd chip select input (csi ). when low, the mcu can access the psd memory and i/ o. when high, the psd memory blocks are disabled to conserve power. the trailing edge of csi can be used to get the psd out of power-down mode. pin name pin type description
psd835g2v 10/98 pd3 2 i/o cmos or open drain pd3 pin of port d. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. input to the plds. pe0 71 i/o cmos or open drain pe0 pin of port e. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address output. tms input for jtag/isp interface. pe1 72 i/o cmos or open drain pe1 pin of port e. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address output. tck input for jtag/isp interface (schmidt trigger). pe2 73 i/o cmos or open drain pe2 pin of port e. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address output. tdi input for jtag/isp interface. pe3 74 i/o cmos or open drain pe3 pin of port e. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address output. tdo input for jtag/isp interface. pe4 75 i/o cmos or open drain pe4 pin of port e. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address output. tstat input for the isp interface. ready/busy for in-circuit parallel programming. pe5 76 i/o cmos or open drain pe5 pin of port e. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address output. t err active low input for isp interface. pe6 77 i/o cmos or open drain pe6 pin of port e. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address output. v stby sram standby voltage input for battery backup sram. pin name pin type description
11/98 psd835g2v pe7 78 i/o cmos or open drain pe7 pin of port e. this port pin can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address output. v baton battery backup indicator output. goes high when power is drawn from an external battery. pf0- pf7 31-38 i/o cmos or open drain pf0 through pf7 pins of port f. this port pins can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. input to the plds. latched address outputs. as address a0-a3 inputs in 80c51xa mode. as data bus port (d07) in non-multiplexed bus configuration. pg0- pg7 8, 30, 49, 50, 70 i/o cmos or open drain pg0 through pg7 pins of port g. this port pins can be configured to have the following functions: mcu i/o ? write to or read from a standard output or input port. latched address outputs. v cc 9, 29, 69 supply voltage gnd 8, 30, 49, 50, 70 ground pins pin name pin type description
psd835g2v 12/98 figure 3. psd block diagram clkin (pd1) clkin clkin pld input bus prog. port port a prog. port port b power mangmt unit 4 mbit primary flash memory 8 sectors vstdby pa0 ? pa7 pb0 ? pb7 prog. port port c prog. port port d pc0 ? pc7 pd0 ? pd2 adio port ad0 ? ad15 prog. mcu bus intrf. cntl0, cntl1, cntl2 address/data/control bus port a & b 8 ext cs to port c or f 24 input macrocells port a ,b & c 82 82 256 kbit secondary flash memory (boot or data) 4 sectors 64 kbit battery backup sram runtime control and i/o registers sram select perip i/o mode selects macrocell feedback or port input csiop flash isp cpld (cpld) 16 output macrocells flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel ( pe6 ) page register embedded algorithm sector selects sector selects global config. & security ai05793b prog. port pf0 ?pf7 port f pg0 ? pg7 prog. port port g prog. port port e pe0 ? pe7 port f
13/98 psd835g2v psd architectural overview psd devices contain several major functional blocks. figure 3., page 12 shows the architecture of the psd device family. the functions of each block are described briefly in the following sec- tions. many of the blocks perform multiple func- tions and are user configurable. memory each of the memory blocks is briefly discussed in the following paragraphs. a more detailed discus- sion can be found in memory blocks, page 21 . the 4mbit (512k x 8) flash memory is the primary memory of the psd. it is divided into 8 equally- sized sectors that are individually selectable. the 256kbit (32k x8) secondary flash memory is divided into 4 equally-sized sectors. each sector is individually selectable. the 64 kbit sram is intended for use as a scratch-pad memory or as an extension to the mcu sram. if an external battery is connected to voltage standby (vstby, pc2), data is retained in the event of power failure. each sector of memory can be located in a differ- ent address space as defined by the user. the ac- cess times for all memory types includes the address latching and dpld decoding time. page register the 8-bit page register expands the address range of the mcu by up to 256 times. the paged address can be used as part of the address space to access external memory and peripherals, or in- ternal memory and i/o. the page register can also be used to change the address mapping of sectors of the flash memories into different mem- ory spaces for iap. plds the device contains two plds, the decode pld (dpld) and the complex pld (cpld), as shown in table 2 , each optimized for a different function. the functional partitioning of the plds reduces power consumption, optimizes cost/performance, and eases design entry. the dpld is used to decode addresses and to generate sector select signals for the psd inter- nal memory and registers. the cpld can imple- ment user-defined logic functions. the dpld has combinatorial outputs. the cpld has 16 output macrocells (omc) and 8 combinatorial outputs. the psd also has 24 input macrocells (imc) that can be configured as inputs to the plds. the plds receive their inputs from the pld input bus and are differentiated by their output destinations, number of product terms, and macrocells. the plds consume minimal power by using pow- er-management design techniques. the speed and power consumption of the pld is controlled by the turbo bit in pmmr0 and other bits in the pmmr2. these registers are set by the mcu at run-time. there is a slight penalty to pld propaga- tion time when invoking the power management features. i/o ports the psd has 52 i/o pins distributed over the sev- en ports (port a, b, c, d, e, f and g). each i/o pin can be individually configured for different func- tions. ports can be configured as standard mcu i/ o ports, pld i/o, or latched address outputs for mcus using multiplexed address/data buses. the jtag pins can be enabled on port e for in- system programming (isp). ports f and g can also be configured as data ports for a non-multi- plexed bus. ports a and b can also be configured as a data port for a non-multiplexed bus. mcu bus interface psd interfaces easily with most 8-bit mcus that have either multiplexed or non-multiplexed ad- dress/data buses. the device is configured to re- spond to the mcu?s control signals, which are also used as inputs to the plds. for examples, please see mcu bus interface examples, page 49 . table 2. pld i/o table 3. jtag signals on port e name inputs outputs product terms decode pld (dpld) 82 17 43 complex pld (cpld) 82 24 150 port e pins jtag signal pe0 tms pe1 tck pe2 tdi pe3 tdo pe4 tstat pe5 terr
psd835g2v 14/98 jtag port in-system programming (isp) can be performed through the jtag signals on port e. this serial in- terface allows complete programming of the entire psd device. a blank device can be completely programmed. the jtag signals (tms, tck, tstat, terr , tdi, tdo) can be multiplexed with other functions on port e. table 3., page 13 indi- cates the jtag pin assignments. in-system programming (isp) using the jtag signals on port e, the entire psd device (memory, logic, configuration) can be pro- grammed or erased without the use of the mcu. in-application re-programming (iap) the primary flash memory can also be pro- grammed in-system by the mcu executing the programming algorithms out of the secondary memory, or sram. since this is a sizable separate block, the application can also continue to operate. the secondary memory can be programmed the same way by executing out of the primary flash memory. the pld or other psd configuration blocks can be programmed through the jtag port or a device programmer. table 4 indicates which programming methods can program different func- tional blocks of the psd. power management unit (pmu) the power management unit (pmu) gives the user control of the power consumption on selected functional blocks based on system requirements. the pmu includes an automatic power-down (apd) unit that turns off device functions during mcu inactivity. the apd unit has a power-down mode that helps reduce power consumption. the psd also has some bits that are configured at run-time by the mcu to reduce power consump- tion of the cpld. the turbo bit in pmmr0 can be reset to 0 and the cpld latches its outputs and goes to sleep until the next transition on its inputs. additionally, bits in pmmr2 can be set by the mcu to block signals from entering the cpld to reduce power consumption. please see power management, page 67 for more details. table 4. methods of programming different functional blocks of the psd functional block jtag/isp device programmer iap primary flash memory yes yes yes secondary flash memory yes yes yes pld array (dpld and cpld) yes yes no psd configuration yes yes no
15/98 psd835g2v development system the psd family is supported by psdsoft, a win- dows-based (95, 98, nt) software development tool. a psd design is quickly and easily produced in a point-and-click environment. the designer does not need to enter hardware description lan- guage (hdl) equations, unless desired, to define psd pin functions and memory map information. the general design flow is shown in figure 4 . ps- dsoft is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. psdsoft directly supports two low cost device pro- grammers form st: psdpro and flashlink (jtag). both of these programmers may be pur- chased through your local distributor/representa- tive, or directly from our web site using a credit card. the psd is also supported by third party de- vice programmers. see our web site for the current list. figure 4. psdsoft development tool define psd pin and node functions st psd programmer *.obj file automatically configures mcu point-and-click definition of psd pin functions, internal nodes and mcu system memory map psdpro, or flashlink (jtag) choose mcu and psd bus interface and other psd attributes. c code generation generate c code specific to psd functions user's choice of microcontroller compiler/linker *.obj file available for 3rd party programmers (conventional or jtag/isp) mcu firmware hex or s-record format ai04918b define general purpose logic in cpld point-and-click definition of combinatorial and registered logic in cpld. access to hdl is available if needed. merge mcu firmware with psd configuration a composite object file is created containing mcu firmware and psd configuration
psd835g2v 16/98 psd register description and address offset table 5 shows the offset addresses to the psd registers relative to the csiop base address. the csiop space is the 256 bytes of address that is allocated by the user to the internal psd registers. table 5 provides brief descriptions of the registers in csiop space. the following section gives a more detailed description. table 5. register address offset note: 1. other registers that are not part of the i/o ports. register name port a port b port c port d port e port f port g other 1 description data in 00 01 10 11 30 40 41 reads port pin as input, mcu i/ o input mode control 32 42 43 selects mode between mcu i/o or address out data out 04 05 14 15 34 44 45 stores data for output to port pins, mcu i/o output mode direction 06 07 14 15 36 46 47 configures port pin as input or output drive select 08 09 18 19 38 48 49 configures port pins as either cmos or open drain on some pins, while selecting high slew rate on other pins. input macrocell 0a 0b 1a reads input macrocells enable out 0c 0d 1c 1b 4c reads the status of the output enable to the i/o port driver output macrocells a 20 read ? reads output of macrocells a write ? loads macrocell flip-flops output macrocells b 21 read ? reads output of macrocells b write ? loads macrocell flip-flops mask macrocells a 22 blocks writing to the output macrocells a mask macrocells b 23 blocks writing to the output macrocells b primary flash protection c0 read only ? primary flash sector protection secondary flash memory protection c2 read only ? psd security and secondary flash memory sector protection jtag enable c7 enables jtag port pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register vm e2 places psd memory areas in program and/or data space on an individual basis. memory_id0 f0 read only ? primary flash memory and sram size memory_id1 f1 read only ? secondary flash memory type and size
17/98 psd835g2v register bit definition all the registers of the psd are included here, for reference. detailed descriptions of these registers can be found in the following sections. table 6. data-in registers ? ports a, b, c, d, e, f, g note: bit definitions (read-only registers): read port pin status when port is in mcu i/o input mode. table 7. data-out registers ? ports a, b, c, d, e, f, g note: bit definitions: latched data for output to port pin when pin is configured in mcu i/o output mode. table 8. direction registers ? ports a, b, c, d, e, f, g note: bit definitions: port pin 0 = port pin is configured in input mode (default). port pin 1 = port pin is configured in output mode. table 9. control registers ? ports e, f, g note: bit definitions: port pin 0 = port pin is configured in mcu i/o mode (default). port pin 1 = port pin is configured in latched address out mode. table 10. drive registers ? ports a, b, d, e, g note: bit definitions: port pin 0 = port pin is configured for cmos output driver (default). port pin 1 = port pin is configured for open drain output driver. table 11. drive registers ? ports c, f note: bit definitions: port pin 0 = port pin is configured for cmos output driver (default). port pin 1 = port pin is configured in slew rate mode. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0
psd835g2v 18/98 table 12. enable-out registers ? ports a, b, c, f note: bit definitions (read-only registers): port pin 0 = port pin is in tri-state driver (default). port pin 1 = port pin is enabled. table 13. input macrocells ? ports a, b, c note: bit definitions (read-only registers): read input macrocell (imc7-imc0) status on ports a, b and c. table 14. output macrocells a register note: bit definitions: write register: load mcella7-mcella0 with 0 or 1. read register: read mcella7-mcella0 output status. table 15. output macrocells b register note: bit definitions: write register: load mcellb7-mcellb0 with 0 or 1. read register: read mcellb7-mcellb0 output status. table 16. mask macrocells a register note: bit definitions: mcella_prot 0 = allow mcella flip-flop to be loaded by mcu (default). mcella_prot 1 = prevent mcella flip-flop from being loaded by mcu. table 17. mask macrocells b register note: bit definitions: mcellb_prot 0 = allow mcellb flip-flop to be loaded by mcu (default). mcellb_prot 1 = prevent mcellb flip-flop from being loaded by mcu. table 18. flash memory protection register note: bit definitions (read-only register): sec_prot 1 = primary flash memory sector is write protected. sec_prot 0 = primary flash memory sector is not write protected. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 imcell 7 imcell 6 imcell 5 imcell 4 imcell 3 imcell 2 imcell 1 imcell 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mcella 7 mcella 6 mcella 5 mcella 4 mcella 3 mcella 2 mcella 1 mcella 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mcellb 7 mcellb 6 mcellb 5 mcellb 4 mcellb 3 mcellb 2 mcellb 1 mcellb 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mcella 7 mcella 6 mcella 5 mcella 4 mcella 3 mcella 2 mcella 1 mcella 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mcellb 7 mcellb 6 mcellb 5 mcellb 4 mcellb 3 mcellb 2 mcellb 1 mcellb 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot
19/98 psd835g2v table 19. flash boot protection register note: bit definitions: sec_prot 1 = secondary flash memory sector is write protected. sec_prot 0 = secondary flash memory sector is not write protected. security_bit 0 = security bit in device has not been set. security_bit 1 = security bit in device has been set. table 20. jtag enable register note: bit definitions: jtag_enable 1 = jtag port is enabled. jtag_enable 0 = jtag port is disabled. table 21. page register note: bit definitions: configure page input to pld. default is pgr7-pgr0=00. table 22. pmmr0 register note: 1. the bits of this register are cleared to zero following power-up. subsequent reset (reset ) pulses do not clear the registers. 2. bit definitions: apd enable 0 = automatic power-down (apd) is disabled. 1 = automatic power-down (apd) is enabled. pld turbo 0 = pld turbo is on. 1 = pld turbo is off, saving power. pld array clk 0 = clkin to the pld and array is connected. every clkin change powers up the pld when turbo bit is off. 1 = clkin to the pld and array is disconnected, saving power. pld mcells clk 0 = clkin to the pld macrocells is connected. 1 = clkin to the pld macrocells is disconnected, saving power. table 23. pmmr2 register note: bit definitions: pld array addr 0 = address a7-a0 are connected to the pld array. 1 = address a7-a0 are blocked from the pld array, saving power. (note: in xa mode, a3-a0 come from pf3-pf0, and a7-a4 come from adio7-adio4) pld array cntl2 0 = cntl2 input to the pld and array is connected. 1 = cntl2 input to the pld and array is disconnected, saving power. pld array cntl1 0 = cntl1 input to the pld and array is connected. 1 = cntl1 input to the pld and array is disconnected, saving power. pld array cntl0 0 = cntl0 input to the pld and array is connected. 1 = cntl0 input to the pld and array is disconnected, saving power. pld array ale 0 = ale input to the pld and array is connected. 1 = ale input to the pld and array is disconnected, saving power. pld array wrh 0 = wrh/dbe input to the pld and array is connected. 1 = wrh/dbe input to the pld and array is disconnected, saving power. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 security_bit not used not used not used sec3_prot sec2_prot sec1_prot sec0_prot bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used not used not used not used not used not used not used jtagenable bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 pgr 7pgr 6pgr 5pgr 4pgr 3pgr 2pgr 1pgr 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used (set to 0) not used (set to 0) pld mcells clk pld array clk pld turbo not used (set to 0) apd enable not used (set to 0) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used (set to 0) pld array wrh pld array ale pld array cntl2 pld array cntl1 pld array cntl0 not used (set to 0) pld array addr
psd835g2v 20/98 table 24. vm register note: 1. on reset, bit1-bit4 are loaded to configurations that are selected by the user in psdsoft. bit0 and bit7 are always clea red on reset. bit0-bit4 are active only when the device is configured in philips 80c51xa mode. 2. bit definitions: sr_code 0 = psen cannot access sram in 80c51xa modes. 1 = psen can access sram in 80c51xa modes. boot_code 0 = psen cannot access secondary nvm in 80c51xa modes. 1 = psen can access secondary nvm in 80c51xa modes. fl_code 0 = psen cannot access primary flash memory in 80c51xa modes. 1 = psen can access primary flash memory in 80c51xa modes. boot_data 0 = rd cannot access secondary nvm in 80c51xa modes. 1 = rd can access secondary nvm in 80c51xa modes. fl_data 0 = rd cannot access primary flash memory in 80c51xa modes. 1 = rd can access primary flash memory in 80c51xa modes. peripheral mode 0 = peripheral mode of port f is disabled. 1 = peripheral mode of port f is enabled. table 25. memory_id0 register note: bit definitions: f_size[3:0] 4h = primary flash memory size is 4 mbit 5h = primary flash memory size is 8mbit s_size[3:0] 0h = there is no sram 1h = sram size is 16 kbit 3 h = sram size is 64 kbit table 26. memory_id1 register note: bit definitions: b_size[3:0] 0h = there is no secondary nvm 2h = secondary nvm size is 256 kbit b_type[1:0] 0h = secondary nvm is flash memory 1h = secondary nvm is eeprom bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 peripheral mode not used (set to 0) not used (set to 0) fl_data boot_data fl_code boot_code sr_code bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 s_size 3 s_size 2 s_size 1 s_size 0 f_size 3 f_size 2 f_size 1 f_size 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used (set to 0) not used (set to 0) b_type 1 b_type 0 b_size 3 b_size 2 b_size 1 b_size 0
21/98 psd835g2v detailed operation as shown in figure 3., page 12 , the psd consists of six major types of functional blocks: memory blocks pld blocks mcu bus interface i/o ports power management unit (pmu) jtag/isp interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. memory blocks the psd has the following memory blocks: ? primary flash memory ? secondary flash memory ?sram the memory select signals for these blocks origi- nate from the decode pld (dpld) and are user- defined in psdsoft. table 27. memory block size and organization primary flash memory secondary flash memory sram sector number sector size (bytes) sector select signal sector size (bytes) sector select signal sram size (bytes) sram select signal 0 64k fs0 8k csboot0 16k rs0 1 64k fs1 8k csboot1 2 64k fs2 8k csboot2 3 64k fs3 8k csboot3 4 64k fs4 5 64k fs5 6 64k fs6 7 64k fs7 total 512k 8 sectors 32k 4 sectors 16k
psd835g2v 22/98 primary flash memory and secondary flash memory description the primary flash memory is divided evenly into eight equal sectors. the secondary flash memory is divided into four equal sectors of eight kbytes each. each sector of either memory block can be separately protected from program and erase cy- cles. flash memory may be erased on a sector-by-sec- tor basis and programmed word-by-word. flash sector erasure may be suspended while data is read from other sectors of the block and then re- sumed after reading. during a program or erase cycle in flash memory, the status can be output on ready/busy (pe4). this pin is set up using psdsoft. memory block select signals the dpld generates the select signals for all the internal memory blocks (see plds, page 35 ). each of the eight sectors of the primary flash memory has a select signal (fs0-fs7) which can contain up to three product terms. each of the four sectors of the secondary flash memory has a se- lect signal (csboot0-csboot3) which can con- tain up to three product terms. having three product terms for each select signal allows a given sector to be mapped in di fferent areas of system memory. when using an mcu with separate pro- gram and data space, these flexible select signals allow dynamic re-mapping of sectors from one memory space to the other before and after iap. upper and lower block in main flash sector the psd835g2?s main flash memory has eight 64-kbyte sectors. the 64-kbyte sector size may cause some difficulty in code mapping for an 8-bit mcu with only 64-kbyte address space. to re- solve this mapping issue, the psd835g2 provides additional logic (see figure 6., page 23 ) for the user to split the 8 sectors such that each sector has a lower and upper 32-kbyte block, and the two blocks can reside in different pages but in the same address range. if your design works with 64kb sectors, you don?t need to configure this logic. if the design requires 32kb blocks in each sector, you need to define a ?fa15? pld equation in psdsoft as the a15 ad- dress input to the main flash module. fa15 con- sists of 3 product terms and will control whether the mcu is accessing the lower or upper 32kb in the selected sector. figure 4 shows an example for flash sector chip select fs0. a typical equation is fa15 = pgr4 of the page register. when pgr4 is 0 (page 00), the lower 32kb is selected. when pgr4 is switched to 1 by the user, the upper 32kb is selected. psdsoft will automatically generate the pld equations shown, based on your point and click selections. if no fa15 equation is defined in psdsoft, the a15 that comes from the mcu address bus will be rout- ed as input to the primary flash memory instead of fa15. the fa15 equation has no impact on the sector erase operation. note: fa15 affects all eight sectors of the primary flash memory simultaneously. you cannot direct fa15 to a particular flash sector only. figure 5. example for flash sector chip select fs0 page = [pgr7... pgr0]; ?page register output ?sector chip select equation fs0 = ((0000h <= address <= 7fffh) & page = 00h) # ?select first 32kb block ((0000h <= address <= 7fffh) & page = 10h); ?select second 32kb block fa15 = pgr4; ?as address a15 input to the primary flash memory ai07652
23/98 psd835g2v figure 6. selecting the upper or lower block in a primary flash memory sector ready/busy (pe4) this signal can be used to output the ready/busy status of the psd. the output on ready/busy (pe4) is a 0 (busy) when flash memory blocks are being written to, or when the flash memory block is being erased. the output is a 1 (ready) when no write or erase cycle is in progress. memory operation the primary flash memory and secondary flash memory are addressed through the mcu bus in- terface. the mcu can access these memories in one of two ways: ? the mcu can execute a typical bus write or read operation just as it would if accessing a ram or rom device using standard bus cy- cles. ? the mcu can execute a specific instruction that consists of several write and read oper- ations. this involves writing specific data pat- terns to special addresses within the flash memory to invoke an embedded algorithm. these instructions are summarized in table 28., page 24 . typically, the mcu can read flash memory using read operations, just as it would read a rom de- vice. however, flash memory can only be altered using specific erase and program instructions. for example, the mcu cannot write a single byte di- rectly to flash memory as it would write a byte to ram. to program a byte into flash memory, the mcu must execute a program instruction, then test the status of the program cycle. this status test is achieved by a read operation or polling ready/busy (pe4). flash memory can also be read by using special instructions to retrieve particular flash device in- formation (sector protect status and id). dpld array fa15 flash memory chip select pins fs0-fs7 primary flash memory sector a15 addr a15 nvm control bit (1) a14-a0 mux ai07653
psd835g2v 24/98 table 28. instructions note: 1. all bus cycles are write bus cycles, except the ones with the ?read? label 2. all values are in hexadecimal: x = don?t care. ra = address of the memory location to be read rd = data read from location ra during the read cycle pa = address of the memory location to be programmed. addresses are latched on the falling edge of write strobe (wr , cntl0). pa is an even address for psd in word programming mode. pd = data to be programmed at location pa. data is latched on the rising edge of write strobe (wr , cntl0) sa = address of the sector to be erased or verified. the sector select pins (fs0-fs7 or csboot0-csboot3) of the sector or whole memory to be erased, or verified, must be active (high). 3. sector select (fs0-fs7 or csboot0-csboot3) signals are active high, and are defined in psdsoft. 4. only address bits a11-a0 are used in instruction decoding. a15-a12 (or a16-a12) are don?t care. 5. no unlock or instruction cycles are required when the device is in the read mode 6. the reset instruction is required to return to the read mode after reading the flash id, or after reading the sector protecti on status, or if the error flag (dq5/dq13) bit goes high. 7. additional sectors to be erased must be written at the end of the sector erase instruction within 80 s. 8. the data is 00h for an unprotected sector, and 01h for a protected sector. in the fourth cycle, the sector select is active, and (a1,a0)=(1,0) 9. the unlock bypass instruction is required prior to the unlock bypass program instruction. 10. the unlock bypass reset flash instruction is required to return to reading memory data when the device is in the unlock bypa ss mode. 11. the system may perform read and program cycles in non-erasing sectors, read the flash id or read the sector protection statu s when in the suspend sector erase mode. the suspend sector erase instruction is valid only during a sector erase cycle. 12. the resume sector erase instruction is valid only during the suspend sector erase mode. 13. the mcu cannot invoke these instructions while executing code from the same flash memory as that for which the instruction i s intended. the mcu must fetch, for example, the code from the secondary flash memory when reading the sector protection status of the primary flash memory. instruction fs0-fs7 or csboot0- csboot3 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read (5) 1 ?read? ra @ rd read primary flash id (6,13) 1 aah@ 555h 55h@ aaah 90h@ 555h read identifier @x01h read sector protection (6,8,13) 1 aah@ 555h 55h@ aaah 90h@ 555h read identifier 00h or 01h @x02h program a flash byte (13) 1 aah@ 555h 55h@ aaah a0h@ 555h pd@ pa flash sector erase (7) 1 aah@ 555h 55h@ aaah 80h@ 555h aah@ 555h 55h@ aaah 30h@ sa 30h (7) @ next sa flash bulk erase 1 aah@ 555h 55h@ aaah 80h@ 555h aah@ 555h 55h@ aaah 10h@ 555h suspend sector erase (11) 1 b0h@ xxxh resume sector erase (12) 1 30h@ xxxh reset (6) 1 f0h@ any address unlock bypass 1 aah@ 555h 55h@ aaah 20h@ 555h unlock bypass program (9) 1 a0h@ xxxh pd@ pa unlock bypass reset (10) 1 90h@ xxxh 00h@ xxxh
25/98 psd835g2v instructions an instruction consists of a sequence of specific operations. each received byte is sequentially de- coded by the psd and not executed as a standard write operation. the instruction is executed when the correct number of bytes is properly received and the time between two consecutive bytes is shorter than the time-out period. some instruc- tions are structured to include read operations af- ter the initial write operations. the instruction must be followed exactly. any in- valid combination of instruction bytes or time-out between two consecutive bytes while addressing flash memory resets the device logic into read mode (flash memory is read like a rom device). the psd supports the instructions summarized in table 28., page 24 : flash memory: erase memory by chip or sector suspend or resume sector erase program a byte reset to read mode read primary flash identifier value read sector protection status bypass these instructions are detailed in table 28 . for ef- ficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or a confirma- tion byte. the coded cycles consist in writing the data aah to address x555h during the first cycle and data 55h to address xaaah during the second cycle unless the bypass instruction feature is used). address signals a15-a12 are don?t care during the instruction write cycles. however, the appropriate sector select (fs0-fs7 or csboot0-csboot3) must be selected. the primary and secondary flash memories have the same instruction set (except for read primary flash identifier). the sector select signals deter- mine which flash memory is to receive and exe- cute the instruction. the primary flash memory is selected if any one of sector select (fs0-fs7) is high, and the secondary flash memory is selected if any one of sector select (csboot0- csboot3) is high. power-up mode the psd internal logic is reset upon power-up to the read mode. sector select (fs0-fs7 and csboot0-csboot3) must be held low, and write strobe (wr , cntl0) high, during power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of write strobe (wr , cntl0). any write cycle initiation is locked when v cc is below v lko . read under typical conditions, the mcu may read the primary flash memory or the secondary flash memory using read operations just as it would a rom or ram device. alternately, the mcu may use read operations to obtain status information about a program or erase cycle that is currently in progress. lastly, the mcu may use instructions to read special data from t hese memory blocks. the following sections describe these read functions. read memory contents primary flash memory and secondary flash memory are placed in the read mode after power- up, chip reset, or a reset flash instruction (see table 28 ). the mcu can read the memory con- tents of the primary flash memory or the second- ary flash memory by using read operations any time the read operation is not part of an instruc- tion. read primary flash identifier the primary flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 28 ). the identifier for the device is e8h. read memory sector protection status the primary flash memory sector protection sta- tus is read with an instruction composed of 4 oper- ations: 3 specific write operations and a read operation (see table 28 ). the read operation pro- duces 01h if the flash memory sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (primary flash memory or secondary flash mem- ory) can also be read by the mcu accessing the flash protection and flash boot protection regis- ters in psd i/o space. see flash memory sector protect, page 31 , for register definitions.
psd835g2v 26/98 read the erase/program status bits the psd provides several status bits to be used by the mcu to confirm the completion of an erase or program cycle of flash memory. these status bits minimize the time that the mcu spends per- forming these tasks and are defined in table 29 . the status bits can be read as many times as needed. for flash memory, the mcu can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. see programming flash memory, page 28 , for details. table 29. status bit note: 1. x = not guaranteed value, can be read either 1 or 0. 2. dq7-dq0 represent the data bus bits, d7-d0. 3. fs0-fs7 and csboot0-csboot3 are active high. functional block fs0-fs7/csboot0- csboot3 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 flash memory v ih data polling to g g l e flag error flag x erase time- out xxx
27/98 psd835g2v data polling flag (dq7) when erasing or programming in flash memory, the data polling flag (dq7) bit outputs the com- plement of the bit being entered for programming/ writing on the dq7 bit. once the program instruc- tion or the write operation is completed, the true logic value is read on the data polling flag (dq7) bit (in a read operation). ? data polling is effective after the fourth write pulse (for a program instruction) or after the sixth write pulse (for an erase instruction). it must be performed at the address being pro- grammed or at an address within the flash memory sector being erased. ? during an erase cycle, the data polling flag (dq7) bit outputs a 0. after completion of the cycle, the data polling flag (dq7) bit outputs the last bit programmed (it is a 1 after erasing). ? if the byte to be programmed is in a protected flash memory sector, the instruction is ig- nored. ? if all the flash memory sectors to be erased are protected, the data polling flag (dq7) bit is reset to 0 for about 100 s, and then returns to the previous addressed byte. no erasure is performed. toggle flag (dq6) the psd offers another way for determining when the flash memory program cycle is completed. during the internal write operation and when ei- ther the fs0-fs7 or csboot0-csboot3 is true, the toggle flag (dq6) bit toggles from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory. when the internal cycle is complete, the toggling stops and the data read on the data bus d0-d7 is the addressed memory byte. the device is now accessible for a new read or write operation. the cycle is finished when two successive reads yield the same output data. ? the toggle flag (dq6) bit is effective after the fourth write pulse (for a program instruction) or after the sixth write pulse (for an erase in- struction). ? if the byte to be programmed belongs to a pro- tected flash memory sector, the instruction is ignored. ? if all the flash memory sectors selected for erasure are protected, the toggle flag (dq6) bit toggles to 0 for about 100 s and then re- turns to the previous addressed byte. error flag (dq5) during a normal program or erase cycle, the error flag (dq5) bit is set to 0. this bit is set to 1 when there is a failure during flash memory byte pro- gram, sector erase, or bulk erase cycle. in the case of flash memory programming, the er- ror flag (dq5) bit indicates the attempt to program a flash memory bit from the programmed state, 0, to the erased state, 1, which is not valid. the error flag (dq5) bit may also indicate a time-out condi- tion while attempting to program a byte. in case of an error in a flash memory sector erase or byte program cycle, the flash memory sector in which the error occurred or to which the pro- grammed byte belongs must no longer be used. other flash memory sectors may still be used. the error flag (dq5) bit is reset after a reset flash instruction. erase time-out flag (dq3) the erase time-out flag (dq3) bit reflects the time-out period allowed between two consecutive sector erase instructions. the erase time-out flag (dq3) bit is reset to 0 after a sector erase cy- cle for a time period of 100 s + 20% unless an ad- ditional sector erase instruction is decoded. after this time period, or when the additional sector erase instruction is decoded, the erase time-out flag (dq3) bit is set to 1.
psd835g2v 28/98 programming flash memory flash memory must be erased prior to being pro- grammed. the mcu may erase flash memory all at once or by-sector. a flash memory sector is erased to all 1s (ffh), and is programmed by set- ting selected bits to 0. although flash memory is erased by-sector, it is programmed word-by- word. the primary and secondary flash memories re- quire the mcu to send an instruction to program a word or to erase sectors (see table 28., page 24 ). once the mcu issues a flash memory program or erase instruction, it must check the status bits for completion. the embedded algorithms that are in- voked inside the psd support several means to provide status to the mcu. status may be checked using any of three methods: data polling, data toggle, or the ready/busy (pe4) output pin. data polling polling on the data polling flag (dq7) bit is a method of checking whether a program or erase cycle is in progress or has completed. figure 7 shows the data polling algorithm. when the mcu issues a program instruction, the embedded algorithm within the psd begins. the mcu then reads the location of the word to be programmed in flash memory to check status. the data polling flag (dq7) bit of this location be- comes the complement of b7 of the original data byte to be programmed. the mcu continues to poll this location, comparing the data polling flag (dq7) bit and monitoring the error flag (dq5) bit. when the data polling flag (dq7) bit matches b7 of the original data, and the error flag (dq5) bit remains 0, the embedded algorithm is complete. if the error flag (dq5) bit is 1, the mcu should test the data polling flag (dq7) bit again since the data polling flag (dq7) bit may have changed si- multaneously with the error flag (dq5) bit (see figure 7 ). the error flag (dq5) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the mcu at- tempted to program a 1 to a bit that was not erased (not erased is logic 0). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to the flash memory with the byte that was intended to be written. when using the data polling method after an erase cycle, figure 7 still applies. however, the data polling flag (dq7) bit is 0 until the erase cy- cle is complete. a 1 on the error flag (dq5) bit in- dicates a time-out condition on the erase cycle; a 0 indicates no error. the mcu can read any loca- tion within the sector being erased to get the data polling flag (dq7) bit and the error flag (dq5) bit. psdsoft generates ansi c code functions which implement these data polling algorithms. figure 7. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369b dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
29/98 psd835g2v data toggle checking the toggle flag (dq6) bit is a method of determining whether a program or erase cycle is in progress or has completed. figure 8 shows the data toggle algorithm. when the mcu issues a program instruction, the embedded algorithm within the psd begins. the mcu then reads the location of the byte to be pro- grammed in flash memory to check status. the toggle flag (dq6) bit of this location toggles each time the mcu reads this location until the embed- ded algorithm is complete. the mcu continues to read this location, checking the toggle flag (dq6) bit and monitoring the error flag (dq5) bit. when the toggle flag (dq6) bit stops toggling (two con- secutive reads yield the same value), and the er- ror flag (dq5) bit remains 0, the embedded algorithm is complete. if the error flag (dq5) bit is 1, the mcu should test the toggle flag (dq6) bit again, since the toggle flag (dq6) bit may have changed simultaneously with the error flag (dq5) bit (see figure 8 ). the error flag (dq5) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the mcu at- tempted to program a 1 to a bit that was not erased (not erased is logic 0). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to flash memory with the byte that was intended to be written. when using the data toggle method after an erase cycle, figure 8 still applies. the toggle flag (dq6) bit toggles until the erase cycle is complete. a 1 on the error flag (dq5) bit indicates a time-out condition on the erase cycle; a 0 indicates no er- ror. the mcu can read any location within the sec- tor being erased to get the toggle flag (dq6) bit and the error flag (dq5) bit. psdsoft generates ansi c code functions which implement these data toggling algorithms. unlock bypass. the unlock bypass instructions allow the system to program bytes to the flash memories faster than using the standard program instruction. the unlock bypass mode is entered by first initiating two unlock cycles. this is followed by a third write cycle containing the unlock by- pass code, 20h (as shown in table 28., page 24 ). the flash memory then enters the unlock bypass mode. a two-cycle unlock bypass program in- struction is all that is required to program in this mode. the first cycle in this instruction contains the unlock bypass program code, a0h. the sec- ond cycle contains the program address and data. additional data is programmed in the same man- ner. these instructions dispense with the initial two unlock cycles required in the standard pro- gram instruction, resulting in faster total flash memory programming. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset flash instructions are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset flash in- struction. the first cycle must contain the data 90h; the second cycle, the data 00h. addresses are don?t care for both cycles. the flash memory then returns to read mode. figure 8. data toggle flowchart read dq5 & dq6 start read dq6 fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle
psd835g2v 30/98 erasing flash memory flash bulk erase the flash bulk erase instruction uses six write operations followed by a read operation of the status register, as described in table 28., page 24 . if any byte of the bulk erase instruc- tion is wrong, the bulk erase instruction aborts and the device is reset to the read flash memory sta- tus. during a bulk erase, the memory status may be checked by reading the error flag (dq5) bit, the toggle flag (dq6) bit, and the data polling flag (dq7) bit, as detailed in programming flash memory, page 28 . the error flag (dq5) bit re- turns a 1 if there has been an erase failure (max- imum number of erase cycles has been executed). it is not necessary to program the memory with 00h because the psd automatically does this be- fore erasing to 0ffh. during execution of the bulk erase instruction, the flash memory does not accept any instructions. flash sector erase the sector erase instruction uses six write oper- ations, as described in table 28., page 24 . addi- tional flash sector erase codes and flash memory sector addresses can be written subse- quently to erase other flash memory sectors in parallel, without further coded cycles, if the addi- tional bytes are transmitted in a shorter time than the time-out period of about 100 s. the input of a new sector erase code restarts the time-out peri- od. the status of the internal timer can be monitored through the level of the erase time-out flag (dq3) bit. if the erase time-out flag (dq3) bit is 0, the sector erase instruction has been received and the time-out period is counting. if the erase time- out flag (dq3) bit is 1, the time-out period has ex- pired and the psd is busy erasing the flash mem- ory sector(s). before and during erase time-out, any instruction other than suspend sector erase and resume sector erase instructions abort the cycle that is currently in progress, and reset the device to read mode. it is not necessary to pro- gram the flash memory sector with 00h as the psd does this automatically before erasing (byte=ffh). during a sector erase, the memory status may be checked by reading the error flag (dq5) bit, the toggle flag (dq6) bit, and the data polling flag (dq7) bit, as detailed in programming flash memory, page 28 . during execution of the erase cycle, the flash memory accepts only reset and suspend sector erase instructions. erasure of one flash memory sector may be suspended, in order to read data from another flash memory sector, and then re- sumed. suspend sector erase when a sector erase cycle is in progress, the sus- pend sector erase instruction can be used to sus- pend the cycle by writi ng 0b0h to any even address when an appropriate sector select (fs0- fs7 or csboot0-csboot3) is high. (see table 28., page 24 ). this allows reading of data from an- other flash memory sector after the erase cycle has been suspended. suspend sector erase is accepted only during an erase cycle and defaults to read mode. a suspend sector erase instruc- tion executed during an erase time-out period, in addition to suspending the erase cycle, terminates the time out period. the toggle flag (dq6) bit stops toggling when the psd internal logic is suspended. the status of this bit must be monitored at an address within the flash memory sector being erased. the toggle flag (dq6) bit stops toggling between 0.1 s and 15 s after the suspend sector erase instruction has been executed. the psd is then automatically set to read mode. if an suspend sector erase instruction was exe- cuted, the following rules apply: ? attempting to read from a flash memory sec- tor that was being erased outputs invalid data. ? reading from a flash sector that was not be- ing erased is valid. ? the flash memory cannot be programmed, and only responds to resume sector erase and reset flash instructions (read is an oper- ation and is allowed). ? if a reset flash instruction is received, data in the flash memory sector that was being erased is invalid. resume sector erase if a suspend sector erase instruction was previ- ously executed, the erase cycle may be resumed with this instruction. the resume sector erase in- struction consists in writing 030h to any even ad- dress while an appropriate sector select (fs0- fs7 or csboot0-csboot3) is high. (see table 28., page 24 .)
31/98 psd835g2v specific features flash memory sector protect each primary and secondary flash memory sector can be separately protected against program and erase cycles. sector protection provides addition- al data security because it disables all program or erase cycles. this mode can be activated through the jtag/isp port or a device programmer. sector protection can be selected for each sector using the psdsoft program. this automatically protects selected sectors when the device is pro- grammed through the jtag port or a device pro- grammer. flash memory sectors can be unprotected to allow updating of their contents us- ing the jtag port or a device programmer. the mcu can read (but cannot change) the sector pro- tection bits. any attempt to program or erase a protected flash memory sector is ignored by the device. the verify operation results in a read of the protected data. the retention of the protection status is thus en- sured. the sector protection status can be read by the mcu through the primary and secondary flash memory protection registers (in the csiop block). see table 18., page 18 and table 19., page 19 . reset flash the reset flash instruction consists of one write cycle (see table 28., page 24 ). it can also be op- tionally preceded by the standard two write decod- ing cycles (writing aah to aaah and 55h to 554h). it must be executed after: ? reading the flash protection status or flash id using the flash instruction. ? an error condition has occurred (and the de- vice has set the error flag (dq5) bit to 1) dur- ing a flash memory program or erase cycle. the reset flash instruction puts the flash memo- ry back into normal read mode immediately. if an error condition has occurred (and the device has set the error flag (dq5) bit to 1) the flash memory is put back into normal read mode within 25 s of the reset flash instruction having been issued. the reset flash instruction is ignored when it is is- sued during a program or bulk erase cycle of the flash memory. the reset flash instruction aborts any on-going sector erase cycle, and returns the flash memory to the normal read mode within 25 s. reset (reset ) signal a pulse on reset (reset ) aborts any cycle that is in progress, and resets the flash memory to the read mode. when the reset occurs during a pro- gram or erase cycle, the flash memory takes up to 25 s to return to the read mode. it is recom- mended that the reset (r eset ) pulse (except for power-up reset, described in power-up reset, page 71 ) be at least 25 s so that the flash memory is always ready for the mcu to fetch the bootstrap instructions after the reset cycle is com- plete. sram the sram is enabled when sram select (rs0) from the dpld is high. sram select (rs0) can contain up to three product terms, allowing flexible memory mapping. the sram can be backed up using an external battery. the external battery should be connected to voltage stand-by (vstby, pe6). if you have an external battery connected to the psd, the con- tents of the sram are retained in the event of a power loss. the contents of the sram are re- tained so long as the battery voltage remains at 2 v or greater. if the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs. pe7 can be configured as an output that indicates when power is being drawn from the external bat- tery. battery-on indicator (vbaton, pe7) is high when the supply voltage falls below the battery voltage and the battery on voltage stand-by (vst- by, pe6) is supplying power to the internal sram. sram select (rs0), voltage stand-by (vstby, pc2) and battery-on indicator (vbaton, pc4) are all configured using psdsoft express configu- ration. the sram select (rs0), vbaton and vstby are all configured using psdsoft.
psd835g2v 32/98 sector select and sram select sector select (fs0-fs7 for primary flash memo- ry, csboot0-csboot3 for secondary flash memory) and sram select (rs0) are all outputs of the dpld. they are setup using psdsoft. the following rules apply to the equations for these sig- nals: 1. primary flash memory and secondary flash memory sector select signals must not be larger than the physical sector size. 2. any primary flash memory sector must not be mapped in the same memory space as another primary flash memory sector. 3. a secondary flash memory sector must not be mapped in the same memory space as another secondary flash memory sector. 4. sram and i/o spaces must not overlap. 5. a secondary flash memory sector may overlap a primary flash memory sector. in case of overlap, priority is given to the secondary flash memory sector. 6. sram and i/o spaces may overlap any other memory sector. priority is given to the sram and i/o. example fs0 is valid when the address is in the range of 8000h to bfffh, csboot0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 always accesses the sram. any address in the range of csboot0 greater than 87ffh (and less than 9fffh) auto- matically addresses secondary flash memory segment 0. any address greater than 9fffh ac- cesses the primary flash memory segment 0. you can see that half of the primary flash memory seg- ment 0 and one-fourth of secondary flash memory segment 0 cannot be accessed in this example. also note that an equation that defined fs1 to any- where in the range of 8000h to bfffh would not be valid. figure 9 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level one has the highest priority and level 3 has the lowest. memory select configuration for mcus with separate program and data spaces the 80c51 and compatible family of mcus have separate address spaces for program memory (selected using program select enable (psen , cntl2)) and data memory (selected using read strobe (rd , cntl1)). any of the memories within the psd can reside in either space or both spaces. this is controlled through manipulation of the vm register that resides in the csiop space. the vm register is set using psdsoft to have an initial value. it can subsequently be changed by the mcu so that memory mapping can be changed on-the-fly. for example, you may wish to have sram and pri- mary flash memory in the data space at boot-up, and secondary flash memory in the program space at boot-up, and later swap the primary and secondary flash memories. this is easily done with the vm register by using psdsoft to configure it for boot-up and having the mcu change it when desired. table 24., page 20 describes the vm register. figure 9. priority level of memory and i/o components level 1 sram, i /o, or peripheral i /o level 2 secondary non-volatile memory highest priority lowest priority level 3 primary flash memory ai02867d
33/98 psd835g2v configuration modes for mcus with separate program and data spaces separate space modes. program space is sep- arated from data space. for example, program select enable (psen , cntl2) is used to access the program code from the primary flash memory, while read strobe (rd , cntl1) is used to access data from the secondary flash memory, sram and i/o port blocks. this configuration requires the vm register to be set to 0ch (see figure 10 ). combined space modes. the program and data spaces are combined into one memory space that allows the primary flash memory, sec- ondary flash memory, and sram to be accessed by either program select enable ( psen , cntl2) or read strobe (rd , cntl1). for example, to configure the primary flash memory in combined space, bits b2 and b4 of the vm register are set to 1 (see figure 11 ). figure 10. 8031 memory modules ? separate space figure 11. 8031 memory modules ? combined space primary flash memory dpld secondary flash memory sram rs0 csboot0-3 fs0-fs7 cs cs cs oe oe rd psen oe ai02869c primary flash memory dpld secondary flash memory sram rs0 csboot0-3 fs0-fs7 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe ai02870c
psd835g2v 34/98 page register the 8-bit page register increases the addressing capability of the mcu by a factor of up to 256. the contents of the register can also be read by the mcu. the outputs of the page register (pgr0- pgr7) are inputs to the dpld decoder and can be included in the sector select (fs0-fs7, csboot0-csboot3), and sram select (rs0) equations. if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the cpld for general logic. see application note an1154 . figure 12 shows the page register. the eight flip- flops in the register are connected to the internal data bus d0-d7. the mcu can write to or read from the page register. the page register can be accessed at address location csiop + e0h. figure 12. page register memory id registers the 8-bit read-only memory status registers are included in the csiop space. the user can deter- mine the memory configuration of the psd device by reading the memory id0 and id1 registers. the contents of the registers are defined in table 25 and table 26., page 20 . reset d0 - d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 dpld and cpld internal selects and logic pld pgr4 pgr5 pgr6 pgr7 ai02871b
35/98 psd835g2v plds the plds bring programmable logic functionality to the psd. after specifying the logic for the plds in psdsoft, the logic is programmed into the de- vice and available upon power-up. the psd contains two plds: the decode pld (dpld), and the complex pld (cpld). the plds are briefly discussed in the next few paragraphs, and in more detail in decode pld (dpld), page 37 , and in complex pld (cpld), page 38 . figure 13., page 36 shows the configuration of the plds. the dpld performs address decoding for select signals for internal components, such as memory, registers, and i/o ports. the cpld can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic. these logic functions can be constructed using the 16 output macrocells (omc), 24 input macrocells (imc), and the and array. the cpld can also be used to generate external chip select (ecs0- ecs2) signals. the and array is used to form product terms. these product terms are specified using psdsoft. an input bus consisting of 82 signals is connected to the plds. the signals are shown in table 30 . the turbo bit in psd the plds in the psd can minimize power con- sumption by switching to standby when inputs re- main unchanged for an extended time of about 70ns. resetting the turbo bit to 0 (bit 3 of pmmr0) automatically places the plds into standby if no inputs are changing. turning the tur- bo mode off increases propagation delays while reducing power consumption. see power management, page 67 , on how to set the tur- bo bit. additionally, five bits are available in pmmr2 to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations. each of the two plds has unique characteristics suited for its applications. they are described in the following sections. table 30. dpld and cpld inputs note: 1. the address inputs are a19-a4 in 80c51xa mode. input source input name number of signals mcu address bus 1 a15-a0 16 mcu control signals cntl2-cntl0 3 reset rst 1 power-down pdn 1 port a input macrocells pa7-pa0 8 port b input macrocells pb7-pb0 8 port c input macrocells pc7-pc0 8 port d inputs pd3-pd0 4 port f inputs pf7-pf0 8 page register pgr7-pgr0 8 macrocell a feedback mcella.fb7-fb0 8 macrocell b feedback mcellb.fb7-fb0 8 secondary flash memory program status bit ready/busy 1
psd835g2v 36/98 figure 13. pld diagram pld input bus 8 input macrocell & input ports direct macrocell input to mcu data bus csiop select sram select secondary non-volatile memory selects decode pld page register peripheral selects jtag select cpld pt alloc. mcella mcellb direct macrocell access from mcu data bus 24 input macrocell (port a,b,c) 16 output macrocell i/o ports primary flash memory selects 12 port d and f inputs to port a to port b data bus 8 8 8 4 1 1 2 1 external chip selects to port c or f 3 73 16 82 24 output macrocell feedback ai02872d
37/98 psd835g2v decode pld (dpld) the dpld, shown in figure 14 , is used for decod- ing the address for internal and external compo- nents. the dpld can be used to generate the following decode signals: ? 8 sector select (fs0-fs7) signals for the pri- mary flash memory (three product terms each) ? 4 sector select (csboot0-csboot3) sig- nals for the secondary flash memory (three product terms each) ? 1 internal sram select (rs0) signal (three product terms) ? 1 internal csiop select (psd configuration register) signal ? 1 jtag select signal (enables jtag/isp on port e) ? 2 internal peripheral select signals (peripheral i/o mode). figure 14. dpld logic array note: 1. the address inputs are a19-a4 in 80c51xa mode. 2. additional address lines can be brought into psd via port a, b, c, d or f. (inputs) (32) (8) (16) (1) pdn (apd output) i /o ports (port a,b,c,f) (8) pgr0 - pgr7 (8) mcella.fb7-fb0 (feedbacks) mcellb.fb7-fb0 (feedbacks) a15-a0 (1,2) (4) (3) pd3-pd0 (ale,clkin,csi) cntrl2-cntrl0 ( read/write control signals) (1) (1) reset rd_bsy rs0 csiop psel0 psel1 8 primary flash memory sector selects sram select i/o decoder select peripheral i/o mode select csboot 0 csboot 1 csboot 2 csboot 3 fs0 fs7 3 3 3 3 3 3 3 3 3 3 3 3 3 jtagsel ai02873e fs1 fs2 fs3 fs6 fs5 fs4
psd835g2v 38/98 complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. the cpld can also be used to generate three external chip se- lect (ecs0-ecs2), routed to port d. although external chip select (ecs0-ecs2) can be produced by any output macrocell (omc), these three external chip select (ecs0-ecs2) on port d do not consume any output macrocells (omc). as shown in figure 13., page 36 , the cpld has the following blocks: 24 input macrocells (imc) 16 output macrocells (omc) macrocell allocator product term allocator and array capable of generating up to 137 product terms four i/o ports. each of the blocks are described in the sections that follow. the input macrocells (imc) and output macrocells (omc) are connected to the psd internal data bus and can be directly accessed by the mcu. this enables the mcu software to load data into the output macrocells (omc) or read data from both the input and output macrocells (imc and omc). this feature allows efficient implementation of sys- tem logic and eliminates the need to connect the data bus to the and array as required in most standard pld macrocell architectures.
39/98 psd835g2v figure 15. macrocell and i/o port i/o ports cpld macrocells input macrocells latched address out mux mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. select input product terms from other macrocells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) macrocell feedback i/o port input ale/as pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select pld input bus pld input bus mcu address / data bus macrocell out to mcu data load control and array cpld output i/o pin ai02874b
psd835g2v 40/98 output macrocell (omc) eight of the output macrocells (omc) are con- nected to port a pins and are named as mcella0- mcella7. the other eight macrocells are connect- ed to port b pins and are named as mcellb0- mcellb7. the output macrocell (omc) architecture is shown in figure 16., page 42 . as shown in the fig- ure, there are native product terms available from the and array, and borrowed product terms avail- able (if unused) from other output macrocells (omc). the polarity of the product term is con- trolled by the xor gate. the output macrocell (omc) can implement either sequential logic, us- ing the flip-flop element, or combinatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the output macrocell (omc) block can be configured as a d, t, jk, or sr type in the psdsoft program. the flip-flop?s clock, preset, and clear inputs may be driven from a product term of the and array. alternatively, clkin (pd1) can be used for the clock input to the flip-flop. the flip-flop is clocked to the rising edge of clkin (pd1). the preset and clear are active high inputs. each clear input can use up to two product terms. table 31. output macrocell port and data bit assignments output macrocell port assignment native product terms maximum borrowed product terms data bit for loading or reading mcella0 port a0 3 6 d0 mcella1 port a1 3 6 d1 mcella2 port a2 3 6 d2 mcella3 port a3 3 6 d3 mcella4 port a4 3 6 d4 mcella5 port a5 3 6 d5 mcella6 port a6 3 6 d6 mcella7 port a7 3 6 d7 mcellb0 port b0 4 5 d0 mcellb1 port b1 4 5 d1 mcellb2 port b2 4 5 d2 mcellb3 port b3 4 5 d3 mcellb4 port b4 4 6 d4 mcellb5 port b5 4 6 d5 mcellb6 port b6 4 6 d6 mcellb7 port b7 4 6 d7
41/98 psd835g2v product term allocator the cpld has a product term allocator. the ps- dsoft uses the product term allocator to borrow and place product terms from one macrocell to an- other. the following list summarizes how product terms are allocated: mcella0-mcella7 all have three native product terms and may borrow up to six more mcellb0-mcellb3 all have four native product terms and may borrow up to five more mcellb4-mcellb7 all have four native product terms and may borrow up to six more. each macrocell may only borrow product terms from certain other macrocells. product terms al- ready in use by one macrocell are not available for another macrocell. if an equation requires more product terms than are available to it, then ?external? product terms are required that consume other output macro- cells (omc). if external product terms are used, extra delay is added for the equation that required the extra product terms. this is called product term expansion. psdsoft performs this expansion as needed. loading and reading the output macrocells (omc). the output macrocells (omc) block oc- cupies a memory location in the mcu address space, as defined by the csiop block (see i/o ports, page 56 ). the flip-flops in each of the 16 output macrocells (omc) can be loaded from the data bus by a mcu. loading the output macro- cells (omc) with data from the mcu takes priority over internal functions. as such, the preset, clear, and clock inputs to the flip-flop can be overridden by the mcu. the ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. data can be loaded to the output macrocells (omc) on the trailing edge of the write strobe (wr , cntl0) signal. the omc mask register there is one mask register for each of the two groups of eight output macrocells (omc). the mask registers can be used to block the loading of data to individual output macrocells (omc). the default value for the mask registers is 00h, which allows loading of the output macrocells (omc). when a given bit in a mask register is set to a 1, the mcu is blocked from writing to the as- sociated output macrocells (omc). for example, suppose mcella0-mcella3 are being used for a state machine. you would not want a mcu write to mcella to overwrite the state machine registers. therefore, you would want to load the mask reg- ister for mcella (mask macrocell ab) with the value 0fh. the output enable of the omc the output macrocells (omc) block can be con- nected to an i/o port pin as a pld output. the out- put enable of each port pin driver is controlled by a single product term from the and array, or?ed with the direction register output. the pin is en- abled upon power-up if no output enable equation is defined and if the pin is declared as a pld out- put in psdsoft. if the output macrocell (omc) output is declared as an internal node and not as a port pin output in the psdabel file, the port pin can be used for other i/o functions. the internal node feedback can be routed as an input to the and array.
psd835g2v 42/98 figure 16. cpld output macrocell pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input macrocell i/o pin internal data bus direction register clear ( .re ) programmable ff ( d / t/jk /sr ) wr enable ( .oe ) preset ( .pr ) rd macrocell cs ai02875c
43/98 psd835g2v input macrocells (imc) the cpld has 24 input macrocells (imc), one for each pin on ports a, b, and c. the architecture of the input macrocells (imc) is shown in figure 17., page 44 . the input macrocells (imc) are indi- vidually configurable, and can be used as a latch, register, or to pass incoming port signals prior to driving them onto the pld input bus. the outputs of the input macrocells (imc) can be read by the mcu through the internal data bus. the enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the cpld and array or the mcu address strobe (ale/as). each product term output is used to latch or clock four input macrocells (imc). port inputs 3-0 can be con- trolled by one product term and 7-4 by another. configurations for the input macrocells (imc) are specified by psdsoft. outputs of the input macro- cells (imc) can be read by the mcu via the imc buffer. see i/o ports, page 56 . input macrocells (imc) can use address strobe (ale/as, pd0) to latch address bits higher than a15. any latched addresses are routed to the plds as inputs. input macrocells (imc) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. figure 18., page 45 shows a typical configuration where the master mcu writes to the port a data out register. this, in turn, can be read by the slave mcu via the activation of the ?slave-read? output enable product term. the slave can also write to the port a input mac- rocells (imc) and the master can then read the in- put macrocells (imc) directly. note that the ?slave-read? and ?slave-wr? signals are product terms that are derived from the slave mcu inputs read strobe (rd , cntl1), write strobe (wr , cntl0), and slave_cs.
psd835g2v 44/98 figure 17. input macrocell output macrocells a and macrocells b pt pt feedback and array pld input bus port driver i/o pin internal data bus direction register mux mux ale/as pt q q d d g latch input macrocell enable ( .oe ) d ff input macrocell _ rd ai02876c
45/98 psd835g2v figure 18. handshaking communication using input macrocells master mcu mcu - rd mcu - rd mcu - wr slave ? wr slave ? cs mcu - wr d [ 7:0 ] d [ 7:0 ] cpld dq qd port a data out register port a input macrocell port a slave ? read slave mcu rd wr ai02877c psd
psd835g2v 46/98 external chip the cpld also provides eight chip select outputs that can be used to select external devices. the chip selects can be routed to either port c or port f, depending on the pin declaration in the psd- soft. each chip select (ecs0-ecs7) consists of one product term that can be configured active high or low. the output enable of the pin is controlled by either the output enable product term or the direction register (see figure 19 ). figure 19. external chip select pld input bus polarity bit pd0 pin ecs pt ecs to port c or f enable (.oe) pt direction register cpld and array ai07654 port c or port f
47/98 psd835g2v mcu bus interface the ?no-glue logic? mcu bus interface block can be directly connected to most popular mcus and their control signals. key 8-bit mcus, with their bus types and control signals, are shown in table 32 . the interface type is specified using the psd- soft. table 32. mcus and their control signals note: 1. unused cntl2 pin can be configured as pld input. other unused pins (pd3-pd0, pa3-pa0) can be configured for other i/o fu nc- tions. 2. ale/as input is optional for mcus with a non-multiplexed bus mcu data bus width cntl0 cntl1 cntl2 pc7 pd0 2 adio0 pa3-pa0 pa7-pa4 8031/8051 8 wr rd psen (note 1 ) ale a0 (note 1 )(note 1 ) 80c51xa 8 wr rd psen (note 1 ) ale a4 a3-a0 (note 1 ) 80c251 8 wr psen (note 1 )(note 1 ) ale a0 (note 1 )(note 1 ) 80c251 8 wr rd psen (note 1 ) ale a0 (note 1 )(note 1 ) 80198 8 wr rd (note 1 )(note 1 ) ale a0 (note 1 )(note 1 ) 68hc11 8 r/w e (note 1 )(note 1 ) as a0 (note 1 )(note 1 ) 68hc05c0 8 wr rd (note 1 )(note 1 ) as a0 (note 1 )(note 1 ) 68hc912 8 r/w e (note 1 ) dbe as a0 (note 1 )(note 1 ) z80 8 wr rd (note 1 )(note 1 )(note 1 ) a0 d3-d0 d7-d4 z8 8 r/w ds (note 1 )(note 1 ) as a0 (note 1 )(note 1 ) 68330 8 r/w ds (note 1 )(note 1 ) as a0 (note 1 )(note 1 ) m37702m2 8 r/w e (note 1 )(note 1 ) ale a0 d3-d0 d7-d4
psd835g2v 48/98 psd interface to a multiplexed 8-bit bus figure 20 shows an example of a system using a mcu with an 8-bit multiplexed bus and a psd. the adio port on the psd is connected directly to the mcu address/data bus. address strobe (ale/as, pd0) latches the address signals internally. latched addresses can be brought out to port e, for g. the psd drives the adio data bus only when one of its internal resources is accessed and read strobe (rd , cntl1) is active. should the system address bus exceed sixteen bits, ports a, b, c, or f may be used as additional address in- puts. figure 20. an example of a typical 8-bit multiplexed bus interface mcu wr rd bhe ale reset ad7-ad0 a15-a8 a15-a8 a7-a0 adio port port f port g port a, b or c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) ( optional ) psd ai02878d a23-a16 (optional)
49/98 psd835g2v psd interface to a non-multiplexed 8-bit bus figure 21 shows an example of a system using a mcu with an 8-bit non-multiplexed bus and a psd. the address bus is connected to the adio port, and the data bus is connected to port f. port f is in tri-state mode when the psd is not access- ed by the mcu. should the system address bus exceed sixteen bits, ports a, b or c may be used for additional address inputs. mcu bus interface examples figures 22 through figure 25., page 55 show ex- amples of the basic connections between the psd and some popular mcus. the psd control input pins are labeled as to the mcu function for which they are configured. the mcu bus interface is specified using the psdsoft. figure 21. an example of a typical 8-bit non-multiplexed bus interface mcu wr rd bhe ale reset d7-d0 a15-a0 a23-a16 d7-d0 adio port port f port g port a, b or c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d (optional) psd ai02879d
psd835g2v 50/98 80c31 figure 22 shows the bus interface for the 80c31, which has an 8-bit multiplexed address/data bus. the lower address byte is multiplexed with the data bus. the mcu control signals program se- lect enable (psen , cntl2), read strobe (rd , cntl1), and write strobe (wr , cntl0) may be used for accessing the internal memory and i/o ports blocks. address strobe (ale/as, pd0) latches the address. figure 22. interfacing the psd with an 80c31 ea/vp x1 x2 reset reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa0 pa2 pa1 pa3 pa4 pa5 pa6 pa7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd3 pd1 (clkin) pd2 (cs) reset rd wr psen ale/p txd rxd reset 31 32 33 34 35 36 37 38 3 39 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 38 37 36 35 34 33 32 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 39 60 40 2 80 1 21 22 23 24 25 26 27 28 psd 80c31 ad7-ad0 21 22 23 24 25 26 27 28 17 16 29 30 a8 a9 a10 a11 a12 a13 a14 a15 rd wr psen ale 10 11 ad [ 7:0 ] reset 51 52 53 54 55 56 57 58 ai02880d crystal ad [15 :8 ] 79 pd0 (ale) pe2 (tdi) pe0 (tms) pe1 (tck/st) 73 71 72 pe5 (terr) pe3 (tdo) pe4 (tstat/rdy) 76 74 75 pe7 (vbaton) pe6 (vstby) 78 77 v cc v cc v cc v cc pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 a15-a8 gnd gnd gnd gnd gnd 70 50 49 30 8
51/98 psd835g2v 80c251 the intel 80c251 mcu features a user-config- urable bus interface with four possible bus config- urations, as shown in table 33 . the first configuration is 80c31 compatible, and the bus interface to the psd is identical to that shown in figure 22., page 50 . the second and third configurations have the same bus connection as shown in table 34., page 52 . there is only one read strobe ( psen ) connected to cntl1 on the psd. the a16 connection to pa0 allows for a larg- er address input to the psd. the fourth configura- tion is shown in figure 23., page 53 . read strobe (rd ) is connected to cntl1 and program select enable (psen ) is connected to cntl2. the 80c251 has two major operating modes: page mode and non-page mode. in non-page mode, the data is multiplexed with the lower ad- dress byte, and address strobe (ale/as, pd0) is active in every bus cycle. in page mode, data (d7- d0) is multiplexed with address (a15-a8). in a bus cycle where there is a page hit, address strobe (ale/as, pd0) is not active and only addresses (a7-a0) are changing. the psd supports both modes. in page mode, the psd bus timing is iden- tical to non-page mode except the address hold time and setup time with respect to address strobe (ale/as, pd0) is not required. the psd access time is measured from address (a7-a0) valid to data in valid. table 33. 80c251 configurations configuration 80c251 read/write pins connecting to psd pins page mode 1 wr rd psen cntl0 cntl1 cntl2 non-page mode, 80c31 compatible a7-a0 multiplex with d7-d0 2 wr psen only cntl0 cntl1 non-page mode a7-a0 multiplex with d7-d0 3 wr psen only cntl0 cntl1 page mode a15-a8 multiplex with d7-d0 4 wr rd psen cntl0 cntl1 cntl2 page mode a15-a8 multiplex with d7-d0
psd835g2v 52/98 table 34. interfacing the psd with the 80c251, with one read input note: 1. the a16 and a17 connections are optional. 2. in non-page-mode, ad7-ad0 connects to adio7-adio0. ea x1 x2 reset reset p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa0 pa2 pa1 pa3 pa4 pa5 pa6 pa7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 adio0 (2) adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd3 pd1 (clkin) pd2 (cs) reset rd/a16 wr psen ale reset 31 32 33 34 35 36 37 38 3 43 35 21 20 2 3 4 5 6 7 8 42 41 40 39 38 37 36 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 39 60 40 2 80 1 21 22 23 24 25 26 27 28 psd 80c31 ad7-ad0 24 25 26 27 28 29 30 31 19 18 32 33 a8 a9 a10 a11 a12 a13 a14 a15 a16 wr rd ale 10 ad [ 7:0 ] reset 51 52 53 54 55 56 57 58 ai02881d crystal ad [15 :8 ] 79 pd0 (ale) pe2 (tdi) pe0 (tms) pe1 (tck/st) 73 71 72 pe5 (terr) pe3 (tdo) pe4 (tstat/rdy) 76 74 75 pe7 (vbaton) pe6 (vstby) 78 77 v cc v cc v cc v cc pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 a17-a8 gnd gnd gnd gnd gnd 70 50 49 30 8 a17 a16 (1) 9 u1 a17
53/98 psd835g2v figure 23. interfacing the psd with the 80c251, with rd and psen inputs ea x1 x2 reset reset p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa0 pa2 pa1 pa3 pa4 pa5 pa6 pa7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 adio0 (2) adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd3 pd1 (clkin) pd2 (cs) reset rd/a16 wr psen ale reset 31 32 33 34 35 36 37 38 3 43 35 21 20 2 3 4 5 6 7 8 42 41 40 39 38 37 36 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 39 60 40 2 80 1 21 22 23 24 25 26 27 28 psd 80c31 ad7-ad0 24 25 26 27 28 29 30 31 19 18 32 33 a8 a9 a10 a11 a12 a13 a14 a15 wr rd ale 10 ad [ 7:0 ] reset 51 52 53 54 55 56 57 58 ai02882d crystal ad [ 15:8 ] 79 pd0 (ale) pe2 (tdi) pe0 (tms) pe1 (tck/st) 73 71 72 pe5 (terr) pe3 (tdo) pe4 (tstat/rdy) 76 74 75 pe7 (vbaton) pe6 (vstby) 78 77 v cc v cc v cc v cc pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 a15-a8 gnd gnd gnd gnd gnd 70 50 49 30 8 9 psen
psd835g2v 54/98 80c51xa the philips 80c51xa mcu family supports an 8- or 16-bit multiplexed bus that can have burst cy- cles. address bits (a3-a0) are not multiplexed, while (a19-a4) are multiplexed with data bits (d15-d0) in 16-bit mode. in 8-bit mode, (a11-a4) are multiplexed with data bits (d7-d0). the 80c51xa can be configured to operate in eight-bit data mode (as shown in figure 24 ). the 80c51xa improves bus throughput and per- formance by exec uting burst cycles for code fetch- es. in burst mode, address a19-a4 are latched internally by the psd, while the 80c51xa changes the a3-a0 signals to fetch up to 16 bytes of code. the psd access time is then measured from ad- dress a3-a0 valid to data in valid. the psd bus timing requirement in burst mode is identical to the normal bus cycle, except the address setup and hold time with respect to address strobe (ale/as, pd0) does not apply. figure 24. interfacing the psd with the 80c51x, 8-bit data bus ea/wait xtal1 xtal2 reset reset rxd0 txd0 rxd1 txd1 t2ex t2 t0 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa0 pa2 pa1 pa3 pa4 pa5 pa6 pa7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 adio0 (2) adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd3 pd1 (clkin) pd2 (cs) reset rd wrl psen ale reset 31 32 33 34 35 36 37 38 3 43 35 21 20 11 13 6 7 9 8 42 41 40 39 38 37 36 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 39 60 40 2 80 1 21 22 23 24 25 26 27 28 psd 80c31 24 25 26 27 28 29 30 31 19 18 32 33 a8 a9 a10 a11 a12 a13 a14 a15 wr rd ale 10 a [3 :0 ] reset 51 52 53 54 55 56 57 58 ai02883d crystal a [ 19:12 ] d[7:0] 79 pd0 (ale) pe2 (tdi) pe0 (tms) pe1 (tck/st) 73 71 72 pe5 (terr) pe3 (tdo) pe4 (tstat/rdy) 76 74 75 pe7 (vbaton) pe6 (vstby) 78 77 v cc v cc v cc v cc pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 gnd gnd gnd gnd gnd 70 50 49 30 8 16 psen 92969 int0 int1 14 15 v cc a3 a2 a1 a0/wrh 5 4 3 2 a3 a2 a1 a0
55/98 psd835g2v 68hc11 figure 25 shows a bus interface to a 68hc11 where the psd is configured in 8-bit multiplexed mode with e and r/w settings. the dpld can be used to generate the read and wr signals for external devices. figure 25. interfacing the psd with a 68hc11 xt ex pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa0 pa2 pa1 pa3 pa4 pa5 pa6 pa7 adio0 (2) adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (r/w) cntl1(rd) cntl2 (e) pd3 pd1 (clkin) pd2 (cs) reset as e reset reset 31 32 33 34 35 36 37 38 3 35 8 7 34 13 42 41 40 39 38 37 36 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 39 60 40 2 80 1 21 22 23 24 25 26 27 28 psd 80c31 ad7-ad0 27 28 29 30 31 6 32 33 a8 a9 a10 a11 a12 a13 a14 a15 r/w a [3 :0 ] reset 51 52 53 54 55 56 57 58 ai02884d crystal a [ 15:8] 79 pd0 (as) pe2 (tdi) pe0 (tms) pe1 (tck/st) 73 71 72 pe5 (terr) pe3 (tdo) pe4 (tstat/rdy) 76 74 75 pe7 (vbaton) pe6 (vstby) 78 77 v cc v cc v cc v cc pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 a15-a8 gnd gnd gnd gnd gnd 70 50 49 30 8 16 reset 92969 irq xirq 14 15 r/w 9 10 11 12 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 pa0 pa2 pa1 pa3 pa4 pa5 pa6 pa7 19 18 pd0 pd2 pd1 pd3 pd4 pd5 49 50 43 44 45 46 47 48 21 22 23 24 25 20 pe2 pe0 pe1 pe5 pe3 pe4 pe7 pe6 vrh vrl 52 51 modb moda 2 3 5 4 e as
psd835g2v 56/98 i/o ports there are seven programmable i/o ports: ports a, b, c, d, e and f. each of the ports is eight bits ex- cept for port d, which is 4 bits. each port pin is in- dividually user-configurable, thus allowing multiple functions per port. the ports are configured using psdsoft or by the mcu writing to on-chip registers in the csiop space. the topics discussed in this section are: general port architecture port operating modes port configuration registers (pcr) port data registers individual port functionality. general port architecture the general architecture of the i/o port block is shown in figure 26., page 57 . individual port ar- chitectures are shown in figure 28., page 63 to figure 30., page 66 . in general, once the purpose for a port pin has been defined, that pin is no long- er available for other purposes. exceptions are noted. as shown in figure 26., page 57 , the ports contain an output multiplexer whose select signals are driven by the configuration bits in the control reg- isters (ports e, f and g only) and psdsoft config- uration. inputs to the multiplexer include the following: ? output data from the data out register ? latched address outputs ? cpld macrocell output ? external chip select (ecs0-ecs2) from the cpld. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the port data buffer (pdb) is connected to the internal data bus for feedback and can be read by the mcu. the data out and macrocell outputs, direc- tion and control registers, and port pin input are all connected to the port data buffer (pdb). the port pin?s tri-state output driver enable is con- trolled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable product term of any of the array outputs is not defined and that port pin is not defined as a cpld output in the psdabel file, then the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the mcu. the port data buffer (pdb) feedback path allows the mcu to check the contents of the registers. ports a, b, and c have embedded input macro- cells (imc). the input macrocells (imc) can be configured as latches, registers, or direct inputs to the plds. the latches and registers are clocked by address strobe (ale/as, pd0) or a product term from the pld and array. the outputs from the input macrocells (imc) drive the pld input bus and can be read by the mcu. see input macrocell, page 44 . port operating modes the i/o ports have several modes of operation. some modes can be defined using psdabel, some by the mcu writing to the registers in csiop space, and some by both. the modes that can only be defined using psdsoft must be pro- grammed into the device and cannot be changed unless the device is reprogrammed. the modes that can be changed by the mcu can be done so dynamically at run-time. the pld i/o, data port, address input, peripheral i/o and mcu reset modes are the only modes that must be defined before programming the device. all other modes can be changed by the mcu at run-time. table 35., page 58 summarizes which modes are available on each port. table 38., page 61 shows how and where the different modes are config- ured. each of the port operating modes are de- scribed in the following sections.
57/98 psd835g2v figure 26. general i/o port architecture internal data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ext cs ale read mux p d b cpld - input control reg. dir reg. input macrocell enable out data in output select output mux port pin data out address ai02885
psd835g2v 58/98 mcu i/o mode in the mcu i/o mode, the mcu uses the i/o ports block to expand its own i/o ports. by setting up the csiop space, the ports on the psd are mapped into the mcu address space. the addresses of the ports are listed in table 5., page 16 . a port pin can be put into mcu i/o mode by writing a 0 to the corresponding bit in the control register (ports e, f and g). the mcu i/o direction may be changed by writing to the corresponding bit in the direction register, or by the output enable product term. see direction register, page 61 . when the pin is configured as an output, the content of the data out register drives the pin. when configured as an input, the mcu can read the port input through the data in buffer. see figure 26., page 57 . ports a, b and c do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if they are specified in psdsoft. pld i/o mode the pld i/o mode uses a port as an input to the cpld?s input macrocells (imc), and/or as an out- put from the cpld?s output macrocells (omc). the output can be tri-stated with a control signal. this output enable control signal can be defined by a product term from the pld, or by resetting the corresponding bit in the direction register to 0. the corresponding bit in the direction register must not be set to 1 if the pin is defined as a pld input pin in psdsoft. the pld i/o mode is speci- fied in psdsoft by declaring the port pins, and then specifying an equation in psdsoft. address out mode for mcus with a multiplexed address/data bus, address out mode can be used to drive latched addresses on to the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direc- tion register and control register must be set to a 1 for pins to use address out mode. this must be done by the mcu at run-time. see table 37., page 59 for the address output pin assign- ments on ports e, f and g for various mcus. note: do not drive address signals with address out mode to an external memory device if it is in- tended for the mcu to boot from the external de- vice. the mcu must first boot from psd memory so the direction and control register bits can be set. table 35. port operating modes note: 1. can be multiplexed with other i/o functions. port mode port a port b port c port d port e port f port g m cu i/ o yes yes yes ye s yes yes ye s pld i/o mcella outputs mcellb outputs additional ext. cs outputs pld inputs yes no no yes no yes no yes no no yes yes no no no ye s no no no no no no yes yes no no no no address out no no no no yes (a7-a0) yes (a7-a0) ye s ( a7-a0 ) or (a15-a8) a ddres s in yes yes yes ye s no yes n o data port no no no no no yes no peripheral i/o no no no no no yes no jtag isp no no no no yes 1 no no
59/98 psd835g2v table 36. port operating mode settings note: 1. n/a = not applicable 2. the direction of the port a,b,c, and f pins are controlled by the direction register or?ed with the individual output enable product term (.oe) from the cpld and array. 3. any of these three methods enables the jtag pins on port e. 4. control register setting is not applicable to ports a, b and c. table 37. i/o port latched address output assignments note: 1. n/a = not applicable. mode defined in psdsoft control register setting direction register setting vm register setting jtag enable mcu i/o declare pins only 0 (note 4 ) 1 = output, 0 = input (note 2 ) n/a n/a pld i/o declare pins and logic equations n/a (note 2 ) n/a n/a data port (port f) selected for mcu with non-mux bus n/a n/a n/a n/a address out (port e, f, g) declare pins only 1 1 (note 2 ) n/a n/a address in (port a,b,c,d, f) declare pins or logic equations for input macrocells n/a n/a n/a n/a peripheral i/o (port f) logic equations (psel0 & 1) n/a n/a pio bit = 1 n/a jtag isp (note 3 ) declare pins only n/a n/a n/a jtag_enable mcu port e (pe3-pe0) port e (pe7-pe4) port f (pf3-pf0) port f (pf7-pf4) port g (pg3-pg0) port g (pg7-pg4) 8051xa n/a 1 address (a7-a4) n/a 1 address (a7-a4) address (a11-a8) address (a15-a12) 80c251 (page mode) n/a n/a n/a n/a address (a11-a8) address (a7-a4) all other 8-bit multiplexed address (a3-a0) address (a7-a4) address (a3-a0) address (a7-a4) address (a3-a0) address (a7-a4) 8-bit non-multiplexed bus n/a n/a n/a n/a address (a3-a0) address (a7-a4)
psd835g2v 60/98 address in mode for mcus that have more than 16 address sig- nals, the higher addresses can be connected to port a, b, c, d or f and are routed as inputs to the plds. the address input can be latched in the in- put macrocell (imc) by address strobe (ale/as, pd0). any input that is included in the dpld equa- tions for the sram, or primary or secondary flash memory is considered to be an address input. data port mode port f can be used as a data bus port for an mcu with a non-multiplexed address/data bus. the data port is connected to the data bus of the mcu. the general i/o functions are disabled in port f if the port is configured as a data port. data port mode is automatically configured in psdsoft when a non-multiplexed bus mcu is selected. peripheral i/o mode peripheral i/o mode can be used to interface with external 8-bit peripherals. in this mode, all of port f serves as a tri-state, bi-directional data buffer for the mcu. peripheral i/o mode is enabled by set- ting bit 7 of the vm register to a 1. figure 27 shows how port a acts as a bi-directional buffer for the mcu data bus if peripheral i/o mode is en- abled. an equation for psel0 and/or psel1 must be written in psdsoft. the buffer is tri-stated when psel0 or psel1 is not active. figure 27. peripheral i/o mode rd psel0 psel1 psel vm register bit 7 wr pf0 - pf7 d0 - d7 data bus ai02886b
61/98 psd835g2v jtag in-system programming (isp) port e is jtag compliant, and can be used for in- system programming (isp). you can multiplex jtag operations with other functions on port e because in-system programming (isp) is not per- formed in normal operating mode. for more infor- mation on the jtag port, see programming in-circuit using the jtag/isp interface, page 73 . port configuration registers (pcr) each port has a set of port configuration regis- ters (pcr) used for configuration. the contents of the registers can be accessed by the mcu through normal read/write bus cycles at the addresses giv- en in table 5., page 16 . the addresses in table 5 are the offsets in hexadecimal from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three port configuration registers (pcr), shown in table 38 , are used for setting the port configurations. the default power-up state for each register in table 38 is 00h. control register any bit reset to 0 in the control register sets the corresponding port pin to mcu i/o mode, and a 1 sets it to address out mode. the default mode is mcu i/o. only ports e, f and g have an associat- ed control register. direction register the direction register, in conjunction with the out- put enable (except for port d), controls the direc- tion of data flow in the i/o ports. any bit set to 1 in the direction register causes the corresponding pin to be an output, and any bit set to 0 causes it to be an input. the default mode for all port pins is input. figure 28., page 63 and figure 29., page 64 show the port architecture diagrams for ports a/b/c and e/f/g, respectively. the direction of data flow for ports a, b, c and f are controlled not only by the direction register, but also by the output enable product term from the pld and array. if the out- put enable product term is not active, the direction register has sole control of a given pin?s direction. an example of a configuration for a port with the three least significant bits set to output and the re- mainder set to input is shown in tabel 41 . since port d only contains four pins (shown in figure 29., page 64 ), the direction register for port d has only the four least significant bits active. drive select register the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corre- sponding bit in the drive select register is set to a 1. the default pin drive is cmos. note that the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates at a high slew rate when the corresponding bit in the drive reg- ister is set to 1. the default rate is slow slew. table 42., page 62 shows the drive register for ports a, b, c, d, e and f. it summarizes which pins can be configured as open drain outputs and which pins the slew rate can be set for. table 38. port configuration registers (pcr) note: 1. see table 42., page 62 for drive register bit definition. table 39. port pin direction control, output enable p.t. not defined table 40. port pin direction control, output enable p.t. defined table 41. port direction assignment example register name port mcu access control e, f, g write/read direction a,b,c,d, e, f, g write/read drive select 1 a,b,c,d, e, f, g write/read direction register bit port pin mode 0 input 1 output direction register bit output enable p. t. port pin mode 0 0 input 0 1 output 1 0 output 1 1 output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 1 1 1
psd835g2v 62/98 table 42. drive register pin assignment note: 1. na = not applicable. port data registers the port data registers, shown in table 43 , are used by the mcu to write data to or read data from the ports. table 43 shows the register name, the ports having each register type, and mcu access for each register type. the registers are described below. data in port pins are connected directly to the data in buff- er. in mcu i/o input mode, the pin input is read through the data in buffer. data out register stores output data written by the mcu in the mcu i/o output mode. the contents of the register are driven out to the pins if the direction register or the output enable product term is set to 1. the contents of the register can also be read back by the mcu. output macrocells (omc) the cpld output macrocells (omc) occupy a lo- cation in the mcu?s address space. the mcu can read the output of the output macrocells (omc). if the omc mask register bits are not set, writing to the macrocell loads data to the macrocell flip-flops. see plds, page 35 for more information. omc mask register each omc mask register bit corresponds to an output macrocell (omc) flip-flop. when the omc mask register bit is set to a 1, loading data into the output macrocell (omc) flip-flop is blocked. the default value is 0 or unblocked. table 43. port data registers drive register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a open drain open drain open drain open drain open drain open drain open drain open drain port b open drain open drain open drain open drain open drain open drain open drain open drain port c slew rate slew rate slew rate slew rate slew rate slew rate slew rate slew rate port d na 1 na 1 na 1 na 1 open drain open drain open drain open drain port e open drain open drain open drain open drain open drain open drain open drain open drain port f slew rate slew rate slew rate slew rate slew rate slew rate slew rate slew rate port g open drain open drain open drain open drain open drain open drain open drain open drain register name port mcu access data in a, b, c, d, e, f, g read ? input on pin data out a, b, c, d, e, f, g write/read output macrocell a, b read ? outputs of macrocells write ? loading macrocell flip-flops mask macrocell a, b write/read ? prevents loading into a given macrocell input macrocell a, b, c read ? outputs of the input macrocells enable out a, b, c, f read ? the output enable control of the port driver
63/98 psd835g2v input macrocells (imc) the input macrocells (imc) can be used to latch or store external inputs. the outputs of the input macrocells (imc) are routed to the pld input bus, and can be read by the mcu. see plds, page 35 . enable out the enable out register can be read by the mcu. it contains the output enable values for a given port. a ?1? indicates the driver is in output mode. a ?0? indicates the driver is in tri-state and the pin is in input mode. ports a,b and c ? functionality and structure ports a and b have similar functionality and struc- ture, as shown in figure 28 . the two ports can be configured to perform one or more of the following functions: ? mcu i/o mode ? cpld output ? macrocells mcella7-mcella0 can be connected to port a, mcellb7-mcellb0 can be connected to port b, external chip se- lect ecs7-ecs0 can be connected to port c. ? cpld input ? via the input macrocells (imc). ? address in ? additional high address inputs using the input macrocells (imc). ? open drain/slew rate ? pins pc7-pc0 can be configured to fast slew rate, pins pa7-pa0 and pb7-pb0 can be configured to open drain mode. figure 28. port a, b and c structure internal data bus data out reg. dq dq wr wr mcella7-mcella0 (port a) mcellb7-mcellb0 (port b) ext.cs (port c) enable product term ( .oe ) read mux p d b cpld - input dir reg. input macrocell enable out data in output select output mux port pin data out ai02887b
psd835g2v 64/98 port d ? functionality and structure port d has four i/o pins. it can be configured to program one or more of the following functions (see figure 29 ): ? mcu i/o mode ? cpld input ? direct input to cpld, no input macrocell (imc). port d pins can be configured in psdsoft as input pins for other dedicated functions: ? pd0 ? ale, as address strobe input. ? pd1 ? clkin, as clock input to the macrocell flip-flops and apd counter. ? pd2 ? csi, as active low chip select input. a high input will disable the flash/sram mem- ories and the csiop. ? pd3 ? as dbe input from 68hc912. figure 29. port d structure internal data bus data out reg. dq dq wr wr read mux p d b cpld - input dir reg. data in output select output mux port d pin data out ai02888c
65/98 psd835g2v port e ? functionality and structure port e can be configured to perform one or more of the following functions: ? mcu i/o mode ? in-system programming ? jtag port can be enabled for programming/erase of the psd device. refer to programming in-cir- cuit using the jtag/isp interface, page 73 for more information. ? open drain ? port e pins can be configured in open drain mode. ? battery backup features ? pe6 can be config- ured as a battery input (v stby ) pin. pe7 can be configured as a battery on indicator output pin, indicating when v cc is less than v bat . ? latched address output ? provided latched address (a7-a0) output. port f ? functionality and structure port f can be configured to perform one or more of the following functions: ? mcu i/o mode ? cpld output ? external chip select ecs7- ecs0 can be connected to port f (or port c). ? cpld input ? as direct input of the cpld ar- ray. ? address in ? addition high address inputs. di- rect input to the cpld array, no input macro- cell (imc) latching is available. ? latched address out ? provide latched ad- dress out per table 47., page 72 . ? slew rate ? pins can be set up for fast slew rate. ? data port ? connected to d7-d0 when port f is configured as data port for a non-multi- plexed bus. ? peripheral i/o mode. port g ? functionality and structure port g can be configured to perform one or more of the following functions: ? mcu i/o mode ? latched address out ? provide latched ad- dress out per table 47., page 72 . ? open drain ? pins can be configured in open drain mode.
psd835g2v 66/98 figure 30. port e, f, g structure internal data bus data out reg. dq d g q dq dq wr wr wr address ext.cs (port f) enable product term ( .oe ) ale read mux p d b cpld - input control reg. dir reg. enable out data in output select output mux port e, f or g pin data out address a7-a0 or a15-a8 ai02889b configuration bit isp or battery back-up (port e)
67/98 psd835g2v power management the psd835g2 offers configurable power saving options. these options may be used individually or in combinations, as follows: ? all memory blocks in a psd (primary and sec- ondary flash memory, and sram) are built with power management technology. in addi- tion to using special silicon design methodolo- gy, power management technology puts the memories into standby mode when address/ data inputs are not changing (zero dc cur- rent). as soon as a transition occurs on an in- put, the affected memory ?wakes up?, changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changing?it hap- pens automatically. the pld sections can also achieve stand-by mode when its inputs are not changing, as described in the sections on the power management mode registers (pmmr). ? as with the power management mode, the au- tomatic power down ( apd) unit allows the psd to reduce to standby current automatical- ly. the apd unit can also block mcu address/ data signals from reaching the memories and plds. this feature is available on all the de- vices of the psd family. the apd unit is de- scribed in more detail in automatic power- down (apd) unit and power-down mode, page 68 . built-in logic monitors the address strobe of the mcu for activity. if there is no activity for a certain time period (mcu is asleep), the apd unit initiates power-down mode (if enabled). once in power-down mode, all address/data signals are blocked from reaching psd memory and plds, and the memories are deselected internally. this allows the memory and plds to remain in standby mode even if the address/data signals are changing state externally (noise, other devices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing states keep the pld out of stand-by mode, but not the memories. ? psd chip select input (csi , pd2) can be used to disable the internal memories, placing them in standby mode even if inputs are changing. this feature does not block any in- ternal signals or disable the plds. this is a good alternative to using the apd unit. there is a slight penalty in memory access time when psd chip select input (csi , pd2) makes its initial transition from deselected to selected. ? the pmmrs can be written by the mcu at run- time to manage power. all psd devices sup- port ?blocking bits? in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figure 34., page 75 ). significant power savings can be achieved by blocking signals that are not used in pld logic equations at run-time. psd- soft creates a fuse map that automatically blocks the low address byte (a7-a0) or the control signals (cntl0-cntl2, ale and wrh/dbe) if none of these signals are used in pld logic equations. psd devices have a turbo bit in pmmr0. this bit can be set to turn the turbo mode off (the default is with turbo mode turned on). while turbo mode is off, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is on. when the turbo mode is on, there is a significant dc current component and the ac component is higher.
psd835g2v 68/98 automatic power-down (apd) unit and power-down mode the apd unit, shown in figure 31 , puts the psd into power-down mode by monitoring the activity of address strobe (ale/as, pd0). if the apd unit is enabled, as soon as activity on address strobe (ale/as, pd0) stops, a four bit counter starts counting. if address strobe (ale/as, pd0) re- mains inactive for fifteen clock periods of clkin (pd1), power-down (pdn) goes high, and the psd enters power-down mode, as discussed next. power-down mode. by default, if you enable the apd unit, power-down mode is automatically en- abled. the device enters power-down mode if ad- dress strobe (ale/as, pd0) remains inactive for fifteen periods of clkin (pd1). the following should be kept in mind when the psd is in power-down mode: ? if address strobe (ale/as, pd0) starts puls- ing again, the psd returns to normal operat- ing mode. the psd also returns to normal operating mode if either psd chip select in- put (csi , pd2) is low or the reset (reset ) input is high. ? the mcu address/data bus is blocked from all memories and plds. ? various signals can be blocked (prior to pow- er-down mode) from entering the plds by set- ting the appropriate bits in the pmmr registers. the blocked signals include mcu control signals and the common clkin (pd1). note that blocking clkin (pd1) from the plds does not block clkin (pd1) from the apd unit. ? all psd memories enter standby mode and are drawing standby current. however, the pld and i/o ports blocks do not go into stand- by mode because you don?t want to have to wait for the logic and i/o to ?wake-up? before their outputs can change. see table 44 for power-down mode effects on psd ports. ? typical standby current is of the order of mi- croamperes. these standby current values assume that there are no transitions on any pld input. table 44. power-down mode?s effect on ports figure 31. apd unit table 45. psd timing and standby current during power-down mode note: 1. power-down does not affect the operation of the pld. the pld operation in this mode is based only on the turbo bit. 2. typical current consumption assuming no pld inputs are changing state and the pld turbo bit is 0. port function pin level mcu i/o no change pld out no change address out undefined data port tri-state peripheral i/o tri-state mode pld propagation delay memory access time access recovery time to normal access 3v v cc typical standby current power-down normal t pd (note 1 ) no access t lvdv 25a (note 2 ) apd en pmmr0 bit 1=1 ale reset csi clkin transition detection edge detect apd counter power down ( pdn ) disable bus interface secondary flash select primary flash select sram select pd clr pd disable primary and secondary flash/sram memories pld select ai02891b
69/98 psd835g2v other power saving options the psd offers other reduced power saving op- tions that are independent of the power-down mode. except for the sram standby and chip se- lect input (csi , pd2) features, they are enabled by setting bits in the pmmr0 and pmmr2 registers (see table 22 and table 23., page 19 for a bit def- inition of the two registers). pld power management the power and speed of the plds are controlled by the turbo bit (bit 3) in pmmr0. by setting the bit to 1, the turbo mode is off and the plds con- sume the specified standby current when the in- puts are not switching for an extended time of 70ns. the propagation delay time is increased af- ter the turbo bit is set to 1 (turned off) when the in- puts change at a composite frequency of less than 15mhz. when the turbo bit is reset to 0 (turned on), the plds run at full power and speed. the turbo bit affects the pld?s dc power, ac power, and propagation delay. refer to maximum rating, page 78 for pld timings. blocking mcu control signals with the bits of pmmr2 can further reduce pld ac power con- sumption. sram standby mode (battery backup). the psd supports a battery backup mode in which the contents of the sram are retained in the event of a power loss. the sram has a voltage standby pin (vstby, pc2) that can be connected to an ex- ternal battery. when v cc becomes lower than v stby then the psd automatically connects to voltage stand-by (vstby, pc2) as a power source to the sram. the sram standby current (i stby ) is typically 0.5a. the sram data reten- tion voltage is 2 v minimum. the battery-on indi- cator (vbaton) can be routed to pe7. this signal indicates when the v cc has dropped below v stby and the sram is running on battery power. psd chip select input (csi , pd2) pd2 of port d can be configured in psdsoft as the psd chip select input (csi ). when low, the sig- nal selects and enables the internal (primary) flash memory, secondary flash memory, sram, and i/o blocks for read or write operations involv- ing the psd. a high on psd chip select input (csi , pd2) disables the primary flash memory, secondary flash memory, and sram, and reduc- es the psd power consumption. however, the pld and i/o signals remain operational when psd chip select input (csi , pd2) is high. there may be a timing penalty when using psd chip select input (csi , pd2) depending on the speed grade of the psd that you are using. see the timing parameter t slqv in table 64., page 90 . input clock the psd provides the option to turn off clkin (pd1) to the pld to save ac power consumption. clkin (pd1) is an input to the pld and array and the output macrocells (omc). during power-down mode, or, if clkin (pd1) is not being used as part of the pld logic equation, the clock should be disabled to save ac power. clkin (pd1) is disconnected from the pld and array or the macrocells block by setting bits 4 or 5 to a 1 in pmmr0. figure 32. enable power-down flow chart enable apd set pmmr0 bit 1 = 1 psd in power down mode ale/as idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bits 4 and 5 and pmmr2 bit 0. ai02892b
psd835g2v 70/98 input control signals the psd provides the option to turn off the ad- dress input (a7-a0) and input control signals (cntl0, cntl1, cntl2, address strobe (ale/ as, pd0) and dbe) to the pld to save ac power consumption. these signals are inputs to the pld and array. during power-down mode, or, if any of them are not being used as part of the pld logic equation, these signals should be disabled to save ac power. they are disconnected from the pld and array by setting bits 0, 2, 3, 4, 5, and 6 to a ?1? in pmmr2. table 46. apd counter operation apd enable bit ale pd polarity ale level apd counter 0 x x not counting 1 x pulsing not counting 1 1 1 counting (generates pdn after 15 clocks) 1 0 0 counting (generates pdn after 15 clocks)
71/98 psd835g2v reset timing and device status at reset power-up reset upon power-up, the psd requires a reset (re- set ) pulse of duration t nlnh-po (1ms minimum) after v cc is steady. during this period, the device loads internal configurations, clears some of the registers and sets the flash memory into operat- ing mode. after the rising edge of reset (reset ), the psd remains in the reset mode for an addi- tional period, t opr (120ns maximum), before the first memory access is allowed. the flash memory is reset to the read mode upon power-up. sector select (fs0-fs7 and csboot0-csboot3) must all be low, write strobe (wr , cntl0) high, during power-up re- set for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of write strobe (wr , cntl0). any flash memory write cycle initiation is prevented automatically when v cc is below v lko . warm reset once the device is up and running, the device can be reset with a pulse of a much shorter duration, t nlnh (150ns minimum). the same t opr period is needed before the device is operational after warm reset. figure 33 shows the timing of the power-up and warm reset. i/o pin, register and pld status at reset table 47., page 72 shows the i/o pin, register and pld status during power-up reset, warm reset and power-down mode. pld outputs are always valid during warm reset, and they are valid in pow- er-up reset once the internal psd configuration bits are loaded. this loading of psd is completed typically long before v cc ramps up to operating level. once the pld is active, the state of the out- puts are determined by the equations specified in psdsoft. reset of flash memory erase and program cycles a reset (reset ) also resets the internal flash memory state machine. during a flash memory program or erase cycle, reset (reset ) termi- nates the cycle and returns the flash memory to the read mode within a period of t nlnh-a (25s minimum). figure 33. power-up and warm reset (reset ) timing t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
psd835g2v 72/98 table 47. status during power-up reset, warm reset and power-down mode note: 1. the sr_cod and periphmode bits in the vm register are always cleared to 0 on power-up reset or warm reset. port configuration power-up reset warm reset power-down mode mcu i/o input mode input mode unchanged pld output valid after internal psd configuration bits are loaded valid depends on inputs to pld (addresses are blocked in pd mode) address out tri-stated tri-stated not defined data port tri-stated tri-stated tri-stated peripheral i/o tri-stated tri-stated tri-stated register power-un reset warm reset power-down mode pmmr0 and pmmr2 cleared to 0 unchanged unchanged macrocells flip-flop status cleared to 0 by internal power-up reset depends on .re and .pr equations depends on .re and .pr equations vm register 1 initialized, based on the selection in psdsoft configuration menu initialized, based on the selection in psdsoft configuration menu unchanged all other registers cleared to 0 cleared to 0 unchanged
73/98 psd835g2v programming in-circuit using the jtag/isp interface the jtag/isp interface block can be enabled on port e (see table 48., page 74 ). all memory blocks (primary and secondary flash memory), pld logic, and psd configuration register bits may be programmed through the jtag/isp inter- face block. a blank device can be mounted on a printed circuit board and programmed using jtag/isp. the standard jtag signals (i eee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr , are optional jtag extensions used to speed up prog ram and erase cycles. by default, on a blank psd (as shipped from the factory or after erasure), four pins on port e are enabled for the basic jtag signals tms, tck, tdi, and tdo . see application note an1153 for more details on jtag in-system programming (isp). standard jtag signals the standard jtag signals (tms, tck, tdi, and tdo) can be enabled by any of three different con- ditions that are logically or?ed. when enabled, tdi, tdo, tck, and tms are inputs, waiting for a jtag serial command from an external jtag con- troller device (such as flashlink or automated test equipment). when the enabling command is received, tdo becomes an output and the jtag channel is fully functional inside the psd. the same command that enables the jtag channel may optionally enable the two additional jtag sig- nals, tstat and terr . the following symbolic logic equation specifies the conditions enabling the four basic jtag signals (tms, tck, tdi, and tdo) on their respective port e pins. for purposes of discussion, the logic label jtag_on is used. when jtag_on is true, the four pins are enabled for jtag. when jtag_on is false, the four pins can be used for general psd i/o. jtag_on = psdsoft_enabled + /* an nvm configuration bit inside the psd is set by the designer in the psdsoft configuration utility. this dedicates the pins for jtag at all times (compliant with ieee 1149.1 */ microcontroller_enabled + /* the microcontroller can set a bit at run-time by writing to the psd register, jtag enable. this register is located at address csiop + offset c7h. setting the jtag_enable bit in this register will enable the pins for jtag use. this bit is cleared by a psd reset or the microcontroller. see table 20., page 19 for bit definition. */ psd_product_term_enabled; /* a dedicated product term (pt) inside the psd can be used to enable the jtag pins. this pt has the reserved name jtagsel. once defined as a node in psdabel, the designer can write an equation for jtagsel. this method is used when the port e jtag pins are multiplexed with other i/o signals. it is recommended to logically tie the node jtagsel to the jen\ signal on the flashlink cable when multiplexing jtag signals. see application note 1153 for details. */ the psd supports jtag/isp commands, but not boundary scan. the psdsoft software tool and flashlink jtag programming cable implement the jtag/isp commands.
psd835g2v 74/98 jtag extensions tstat and terr are two jtag extension signals enabled by an jtag command received over the four standard jtag signals (tms, tck, tdi, and tdo). they are used to speed program and erase cycles by indicating status on psd signals instead of having to scan the status out serially using the standard jtag channel. see application note an1153 . terr indicates if an error has occurred when erasing a sector or programming a byte in flash memory. this signal goes low (active) when an error condition occurs, and stays low until a spe- cial jtag command is executed or a chip reset (reset ) pulse is received after an ?isc_disable? command. tstat behaves the same as ready/busy de- scribed in ready/busy (pe4), page 23 . tstat is high when the psd device is in read mode (pri- mary and secondary flash memory contents can be read). tstat is low when flash memory pro- gram or erase cycles are in progress, and also when data is being written to the secondary flash memory. tstat and terr can be configured as open- drain type signals during a jtag command. security and flash memory protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program, erase and verify commands are blocked. full chip erase returns the part to a non-secured blank state. the security bit can be set in psdsoft. all primary and secondary flash memory sectors can individually be sector protected against era- sures. the sector protect bits can be set in psd- soft. table 48. jtag port signals port e pin jtag signals description pe0 tms mode select pe1 tck clock pe2 tdi serial data in pe3 tdo serial data out pe4 tstat status pe5 terr error flag
75/98 psd835g2v ac/dc parameters the tables provided below describe the ad and dc parameters of the psd: ? dc electrical specification ? ac timing specification pld timing ? combinatorial timing ? synchronous clock mode ? asynchronous clock mode ? input macrocell timing mcu timing ? read timing ?write timing ? peripheral mode timing ? power-down and reset timing the following are issues concerning the parame- ters presented: in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd is in each mode. also, the supply power is considerably different if the turbo bit is 0. the ac power component gives the pld, flash memory, and sram ma/mhz specification. figure 34 show the pld ma/ mhz as a function of the number of product terms (pt) used. in the pld timing parameters, add the required delay when turbo bit is 0. figure 34. pld i cc /frequency consumption 0 20 30 40 60 v cc = 3v 50 010 15 5 20 25 highest composite frequency at pld inputs (mhz) i cc ? (ma) t u r b o o n (1 0 0 % ) turbo on (25%) turbo off t u r b o o f f 10 pt 100% pt 25% ai07656
psd835g2v 76/98 table 49. example of psd typical power calculation at v cc = 3.0v (with turbo mode on) conditions highest composite pld input frequency (freq pld) = 8mhz mcu ale frequency (freq ale) = 4mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power-down mode = 90% number of product terms used (from fitter report) = 54 pt % of total product terms = 54/217 = 25% turbo mode = on calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 1.2ma/mhz x freq ale + %sram x 0.8ma/mhz x freq ale + % pld x 1.1ma/mhz x freq pld + #pt x 200a/pt) = 50a x 0.90 + 0.1 x (0.8 x 1.2ma/mhz x 4mhz + 0.15 x 0.8ma/mhz x 4mhz + 1.1ma/mhz x 8mhz + 54 x 0.2ma/pt) = 45a + 0.1 x (3.84 + 0.48 + 8.8 + 10.8) = 45a + 0.1 x 23.92 = 45a + 2.39ma = 2.43ma this is the operating power with no flash memory program or erase cycles in progress. calculation is based on i out = 0ma.
77/98 psd835g2v table 50. example of psd typical power calculation at v cc = 3.0 v (with turbo mode off) conditions highest composite pld input frequency (freq pld) = 8mhz mcu ale frequency (freq ale) = 4mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power-down mode = 90% number of product terms used (from fitter report) = 54 pt % of total product terms = 54/217 = 25% turbo mode = off calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 1.2ma/mhz x freq ale + %sram x 0.8ma/mhz x freq ale + % pld x (from graph using freq pld)) = 50a x 0.90 + 0.1 x (0.8 x 1.2ma/mhz x 4mhz + 0.15 x 0.8ma/mhz x 4mhz + 15ma) = 45a + 0.1 x (3.84 + 0.48 + 15) = 45a + 0.1 x 18.84 = 45a + 1.94ma = 1.98ma this is the operating power with no flash memory program or erase cycles in progress. calculation is based on i out = 0ma.
psd835g2v 78/98 maximum rating stressing the device above the rating listed in the absolute maximum ratings? table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 51. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 125 c t lead lead temperature during soldering (20 seconds max.) 1 235 c v io input and output voltage (q = v oh or hi-z) ?0.6 4.0 v v cc supply voltage ?0.6 4.0 v v pp device programmer supply voltage ?0.6 14.0 v v esd electrostatic discharge voltage (human body model) 2 ?2000 2000 v
79/98 psd835g2v ac and dc parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 52. operating conditions table 53. ac signal letters for pld timing note: example: t avlx = time from address valid to ale invalid. table 54. ac signal behavior symbols for pld timing note: example: t avlx = time from address valid to ale invalid. table 55. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. table 56. capacitance note: 1. sampled only, not 100% tested. 2. typical values are for t a = 25c and nominal supply voltages. symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a ambient operating temperature (industrial) ?40 85 c ambient operating temperature (commercial) 0 70 c a address input c ceout output d input data e e input g internal wdog_on signal i interrupt input l ale input n reset input or output p port signal output qoutput data rwr , uds , lds , ds , iord, psen inputs s chip select input tr/w input w internal pdn signal b v stby output m output macrocell ttime l logic level low or ale h logic level high v valid x no longer a valid logic level zfloat pw pulse width symbol parameter min. max. unit c l load capacitance 30 pf symbol parameter test condition typ. 2 max. unit c in input capacitance (for input pins) v in = 0v 46 pf c out output capacitance (for input/ output pins) v out = 0v 812 pf c vpp capacitance (for cntl2/v pp )v pp = 0v 18 25 pf
psd835g2v 80/98 figure 35. ac measurement i/o waveform figure 36. ac measurement load circuit figure 37. switching waveforms ? key 3.0v 0v test point 1.5v ai03103b device under test 2.01 v 195 ? c l = 30 pf (including scope and jig capacitance) ai03104b waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102
81/98 psd835g2v table 57. dc characteristics note: 1. reset (reset ) has hysteresis. v il1 is valid at or below 0.2v cc ?0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected or internal power-down mode is active. 3. pld is in non-turbo mode, and none of the inputs are switching. 4. please see figure 34., page 75 for the pld current calculation. 5. i out = 0 symbol parameter test condition (in addition to those in table 52., page 79 ) min. typ. max. unit v ih input high voltage 3.0v < v cc < 3.6v 0.7v cc v cc +0.5 v v il input low voltage 3.0v < v cc < 3.6v ?0.5 0.8 v v ih1 reset high level input voltage (note 1 ) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (note 1 ) ?0.5 0.2v cc ? 0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 1.5 2.3 v v ol output low voltage i ol = 20a, v cc = 3.0v 0.01 0.1 v i ol = 4, v cc = 3.0v 0.15 0.45 v v oh output high voltage except v stby on i oh = ?20a, v cc = 3.0v 2.9 2.99 v i oh = ?1, v cc = 3.0v 2.7 2.8 v v oh1 output high voltage v stby on i oh1 = ?1a v stby ? 0.8 v v stby sram standby voltage 2.0 v cc v i stby sram standby current (vstby pin) v cc = 0 v 0.5 1 a i idle idle current (vstby input) v cc > v stby ?0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb stand-by supply current for power-down mode csi >v cc ?0.3 v (notes 2,3 ) 50 100 a i li input leakage current v ss < v in < v cc ?1 0.1 1 a i lo output leakage current 0.45 < v in < v cc ?10 5 10 a i cc (dc) (note 5 ) operating supply current pld only zpld_turbo = off, f = 0mhz (note 3 ) 0ma zpld_turbo = on, f = 0mhz 400 700 a/pt flash memory during flash memory write/ erase only 10 25 ma read only, f = 0mhz 0 0 ma sram f = 0mhz 0 0 ma i cc (ac) (note 5 ) pld ac base (note 4 ) figure 34 flash memory ac adder 1.5 2.0 ma/ mhz sram ac adder 0.8 1.5 ma/ mhz
psd835g2v 82/98 figure 38. input to output disable / enable figure 39. combinatorial timing ? pld table 58. cpld combinatorial timing note: 1. fast slew rate output available on ports c and f. symbol parameter conditions -90 -12 pt aloc tu rbo off slew rate 1 unit min max min max t pd cpld input pin/feedback to cpld combinatorial output 38 43 + 4 + 20 ? 6 ns t ea cpld input to cpld output enable 43 45 + 20 ? 6 ns t er cpld input to cpld output disable 43 45 + 20 ? 6 ns t arp cpld register clear or preset delay 38 43 + 20 ? 6 ns t arpw cpld register clear or preset pulse width 28 30 + 20 ns t ard cpld array delay any macrocell 23 27 + 4 ns ter tea input input to output enable/disable ai02863 tpd cpld output cpld input ai07655
83/98 psd835g2v table 59. cpld macrocell synchronous clock mode timing note: 1. fast slew rate output available on ports c and f. 2. clkin (pd1) t clcl = t ch + t cl . table 60. cpld macrocell asynchronous clock mode timing symbol parameter conditions -90 -12 pt aloc tur bo off slew rate 1 unit min max min max f max maximum frequency external feedback 1/(t s +t co ) 24.3 20.4 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co ?10) 32.2 25.6 mhz maximum frequency pipelined data 1/(t ch +t cl ) 45.0 35.7 mhz t s input setup time 18 23 + 4 + 20 ns t h input hold time 0 0 ns t ch clock high time clock input 11 14 ns t cl clock low time clock input 11 14 ns t co clock to output delay clock input 23 26 ? 6 ns t ard cpld array delay any macrocell 23 27 + 4 ns t min minimum clock period 2 t ch +t cl 22 28 ns symbol parameter conditions -90 -12 pt aloc turbo off slew rate unit min max min max f maxa maximum frequency external feedback 1/(t sa +t coa ) 23.8 20.8 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa ?10) 31.25 26.3 mhz maximum frequency pipelined data 1/(t cha +t cla ) 38.4 30.3 mhz t sa input setup time 8 10 + 4 + 20 ns t ha input hold time 10 12 ns t cha clock input high time 15 18 + 20 ns t cla clock input low time 12 15 + 20 ns t coa clock to output delay 34 38 + 20 ? 6 ns t arda cpld array delay any macrocell 23 27 + 4 ns t mina minimum clock period 1/f cnta 32 38 ns
psd835g2v 84/98 figure 40. synchronous clock mode timing ? pld figure 41. asynchronous reset / preset figure 42. asynchronous clock mode timing (product term clock) t ch t cl t co t h t s clkin input registered output ai02860 tarp register output tarpw reset/preset input ai02864 tcha tcla tcoa tha tsa clock input registered output ai02859
85/98 psd835g2v figure 43. input macrocell timing (product term clock) table 61. input macrocell timing note: 1. inputs from port a, b, and c relative to register/ latch clock from the pld. ale/as latch timings refer to t avlx and t lxax . symbol parameter conditions -90 -12 pt aloc turbo off unit min max min max t is input setup time (note 1 ) 00 ns t ih input hold time (note 1 ) 20 23 + 20 ns t inh nib input high time (note 1 ) 13 13 ns t inl nib input low time (note 1 ) 12 13 ns t ino nib input to combinatorial delay (note 1 ) 46 62 + 4 + 20 ns t inh t inl t ino t ih t is pt clock input output ai03101
psd835g2v 86/98 figure 44. read timing note: 1. t avlx and t lxax are not required for 80c51xa in burst mode. t avlx t lxax 1 t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale /as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) e r/w ai02895
87/98 psd835g2v table 62. read timing note: 1. rd timing has the same timing as ds and psen signals. 2. rd and psen have the same timing for 80c51. 3. any input used to select an internal psd function. 4. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 5. rd timing has the same timing as ds signal. symbol parameter conditions -90 -12 turbo off unit min max min max t lvlx ale or as pulse width 22 24 ns t avlx address setup time (note 3 ) 79 ns t lxax address hold time (note 3 ) 810 ns t avqv address valid to data valid (note 3 ) 90 120 + 20 ns t slqv cs valid to data valid 90 120 ns t rlqv rd to data valid 8-bit bus (note 5 ) 35 35 ns rd or psen to data valid 8-bit bus, 8031, 80251 (note 2 ) 45 48 ns t rhqx rd data hold time (note 1 ) 00 ns t rlrh rd pulse width (note 1 ) 36 40 ns t rhqz rd to data high-z (note 1 ) 38 40 ns t ehel e pulse width 38 42 ns t theh r/w setup time to enable 10 16 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to address output delay (note 4 ) 30 35 ns
psd835g2v 88/98 figure 45. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlmv t wlwh t dv wh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale / as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi wr (ds) e r/ w ai02896
89/98 psd835g2v table 63. write timing note: 1. any input used to select an internal psd function. 2. in multiplexed mode, latched address generated from adio delay to address output on any port. 3. wr has the same timing as e and ds signals. 4. assuming data is stable before active write signal. 5. assuming write is active before data becomes valid. 6. t whax2 is the address hold time for dpld inputs that are used to generate sector select signals for internal psd memory. 7. t whdx is 11ns when writing to output macrocell registers ab and bc. symbol parameter conditions -90 -12 unit min max min max t lvlx ale or as pulse width 22 24 ns t avlx address setup time (note 1 ) 79ns t lxax address hold time (note 1 ) 810ns t avwl address valid to leading edge of wr (notes 1,3 ) 15 18 ns t slwl cs valid to leading edge of wr (note 3 ) 15 18 ns t dvwh wr data setup time (note 3 ) 40 45 ns t whdx wr data hold time (note 3,7 ) 58ns t wlwh wr pulse width (note 3 ) 40 45 ns t whax1 trailing edge of wr to address invalid (note 3 ) 810ns t whax2 trailing edge of wr to dpld address invalid (note 3,6 ) 00ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3 ) 33 33 ns t dvmv data valid to port output valid using macrocell register preset/clear (notes 3,5 ) 65 70 ns t avpv address input valid to address output delay (note 2 ) 65 68 ns t wlmv wr valid to port output valid using macrocell register preset/clear (notes 3,4 ) 30 35 ns
psd835g2v 90/98 figure 46. peripheral i/o read timing table 64. port f peripheral data mode read timing symbol parameter conditions -90 -12 turbo off unit min max min max t avqv?pf address valid to data valid (note 3 ) 50 50 + 20 ns t slqv?pf csi valid to data valid 35 40 + 20 ns t rlqv?pf rd to data valid (notes 1,4 ) 35 40 ns rd to data valid 8031 mode 45 45 ns t dvqv?pf data in to data out valid 34 38 ns t qxrh?pf rd data hold time 0 0 ns t rlrh?pf rd pulse width (note 1 ) 35 36 ns t rhqz?pf rd to data high-z (note 1 ) 38 40 ns t qxrh ( pf) t rlqv ( pf) t rlrh ( pf) t dvqv ( pf) t rhqz ( pf) t slqv ( pf) t avqv ( pf) address data valid ale /as a /d bus rd data on port f csi ai02897b
91/98 psd835g2v figure 47. peripheral i/o write timing table 65. port f peripheral data mode write timing note: 1. rd has the same timing as ds and psen . 2. wr has the same timing as the e and ds signals. 3. any input used to select port f data peripheral mode. 4. data is already stable on port f. 5. data stable on adio pins to data on port f. table 66. program, write and erase times note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid tq7vqv time units before the data byte, dq0-dq7, is valid for reading. symbol parameter conditions -90 -12 unit min max min max t wlqv?pf wr to data propagation delay (note 2 ) 40 43 ns t dvqv?pf data to port a data propagation delay (note 5 ) 35 38 ns t whqz?pf wr invalid to port a tri-state (note 2 ) 33 33 ns symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase 1 (pre-programmed to 00) 330s flash bulk erase (not pre-programmed) 10 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed to 00) 2.2 s t whqv1 byte program 14 1200 s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) 2 30 ns tdvqv (pf) twlqv (pf) twhqz (pf) address data out a /d bus wr port f data out ale /as ai02898b
psd835g2v 92/98 table 67. power-down timing note: 1. t clcl is the period of clkin (pd1). figure 48. reset (reset ) timing table 68. reset (reset ) timing note: 1. reset (reset ) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles. table 69. v stbyon timing note: 1. v stbyon timing is measured at v cc ramp rate of 2 ms. symbol parameter conditions -90 -12 unit min max min max t lvdv ale access time from power-down 128 135 ns t clwh maximum delay from apd enable to internal pdn valid signal using clkin (pd1) 15 * t clcl 1 s symbol parameter conditions min max unit t nlnh reset active low time 1 300 ns t nlnh?po power up reset active low time 1 ms t nlnh?a warm reset 2 25 s t opr reset high to operational device 300 ns symbol parameter conditions min typ max unit t bvbh v stby detection to v stbyon output high (note 1 ) 20 s t bxbl v stby off detection to v stbyon output low (note 1 ) 20 s t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
93/98 psd835g2v figure 49. isc timing table 70. isc timing note: 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. symbol parameter conditions -90 -12 unit min max min max t isccf clock (tck, pc1) frequency (except for pld) (note 1 ) 15 12 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1 ) 30 40 ns t isccl clock (tck, pc1) low time (except for pld) (note 1 ) 30 40 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2 ) 22mhz t iscchp clock (tck, pc1) high time (pld only) (note 2 ) 240 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2 ) 240 240 ns t iscpsu isc port set up time 11 12 ns t iscph isc port hold up time 5 5 ns t iscpco isc port clock to output 26 32 ns t iscpzv isc port high-impedance to valid output 26 32 ns t iscpvz isc port valid output to high-impedance 26 32 ns iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpvz t iscpzv t iscpco t ai02865
psd835g2v 94/98 package mechanical figure 50. tqfp80 - 80 lead plastic quad flatpack, package outline note: drawing is not to scale. table 71. tqfp80 - 80 lead plastic quad flatpack, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 3.5 0.0 7.0 3.5 0.0 7.0 b 0.22 0.17 0.27 0.009 0.007 0.011 c 0.09 0.20 0.004 0.008 d 14.00 0.551 d1 12.00 0.472 d2 9.50 0.374 e 14.00 0.551 e1 12.00 0.472 e2 9.50 0.374 e 0.50 0.020 l 0.60 0.45 0.75 0.024 0.018 0.030 l1 1.00 0.039 cp 0.08 0.003 n80 80 nd 20 20 ne 20 20 qfp-a nd e1 cp b e a2 a n l a1 d1 d 1 e ne c d2 e2 l1
95/98 psd835g2v part numbering table 72. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: psd8 3 5 g 2 v ? 90 u i t device type psd8 = 8-bit psd with register logic sram size 3 = 64 kbit flash memory size 5 = 4 mbit (512 kb x8) i/o count g = 52 i/o 2nd flash memory 2 = 256 kbit (32 kb x8) flash memory operating voltage v = v cc = 3.0 to 3.6v speed 90 = 90ns 120 = 120ns package u = tqfp80 temperature range blank = 0 to 70c (commercial) i = ?40 to 85c (industrial) shipping option t = tape & reel packing
psd835g2v 96/98 appendix a. pin assignments table 73. psd835g2v tqfp80 pin no. pin assignments pin no. pin assignments pin no. pin assignments pin no. pin assignments 1 pd2 21 pg0 41 pc0 61 pb0 2 pd3 22 pg1 42 pc1 62 pb1 3 ad0 23 pg2 43 pc2 63 pb2 4 ad1 24 pg3 44 pc3 64 pb3 5 ad2 25 pg4 45 pc4 65 pb4 6 ad3 26 pg5 46 pc5 66 pb5 7 ad4 27 pg6 47 pc6 67 pb6 8 gnd 28 pg7 48 pc7 68 pb7 9 v cc 29 v cc 49 gnd 69 v cc 10 ad5 30gnd 50gnd 70gnd 11 ad6 31 pf0 51 pa0 71 pe0 12 ad7 32 pf1 52 pa1 72 pe1 13 ad8 33 pf2 53 pa2 73 pe2 14 ad9 34 pf3 54 pa3 74 pe3 15 ad10 35 pf4 55 pa4 75 pe4 16 ad11 36 pf5 56 pa5 76 pe5 17 ad12 37 pf6 57 pa6 77 pe6 18 ad13 38 pf7 58 pa7 78 pe7 19 ad14 39 reset 59 cntl0 79 pd0 20 ad15 40 cntl2 60 cntl1 80 pd1
97/98 psd835g2v revision history table 74. document revision history date version description of revision 31-may-04 1.0 document reformatted; split from original with both voltage options
psd835g2v 98/98 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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